Processing Vector Instructions
OwnerPeter Vrabel, Sudheendra Srivathsa +2inventors
InventorsPeter Vrabel, Sudheendra Srivathsa, Selina Hopton, Ju MIn Yeoh
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Abstract
A handshaking protocol is implemented between a control unit, a vector processing unit (VPU) and a load-store unit (LSU). Micro-ops of an instruction will only be executed by the LSU if it is guaranteed not to generate an exception and no earlier micro-ops will generate an exception. The handshaking protocol guarantees this using signals passed between the control unit, VPU and LSU.
Claims19
A computer-implemented method of processing instructions by a processing system, wherein the processing system comprises a control unit, a vector processing unit, VPU, and a load-store unit (LSU), wherein the method comprises, for a current instruction to be processed:
- determining, by the control unit, that there are no reasons internal to the control unit that are preventing the current instruction from making architectural updates, and in response sending, to the VPU, an allow signal associated with the current instruction;
- sending, from the VPU to the LSU, one or more respective micro-operations of the current instruction and one or more respective allow signals associated with the respective micro-operation, wherein the one or more respective micro-operations are sent to the LSU in an order;
- for each of a set of the one or more respective micro-operations having an associated respective allow signal, the LSU determining whether the respective micro-operation will generate a respective exception, and sending respective exception information to the VPU, the respective exception information indicating whether the respective micro-operation will generate a respective exception;
- and
- for each respective micro-operation that has i) an associated respective allow signal, ii) respective exception information indicating that the respective micro-operation will not generate an exception, and iii) no earlier respective micro-operations positioned earlier in the order that has respective exception information indicating that the earlier respective micro-operation will generate an exception, sending, by the VPU to the LSU, a respective commit signal associated with the respective micro-operation, wherein the LSU is configured to only execute a respective micro-operation upon receipt of a respective commit signal.
A computer program embodied on a non-transitory computer-readable storage medium and configured so as to cause, when run on a processing system comprising a control unit, a vector processing unit (VPU) and a load-store unit (LSU), the processing system to, for a current instruction to be processed:
- determine, by the control unit, that there are no reasons internal to the control unit that are preventing the current instruction from making architectural updates, and in response sending, to the VPU, an allow signal associated with the current instruction;
- send, from the VPU to the LSU, one or more respective micro-operations of the current instruction and one or more respective allow signals associated with the respective micro-operation, wherein the one or more respective micro-operations are sent to the LSU in an order;
- for each of a set of the one or more respective micro-operations having an associated respective allow signal, the LSU determining whether the respective micro-operation will generate a respective exception, and sending respective exception information to the VPU, the respective exception information indicating whether the respective micro-operation will generate a respective exception;
- and
- for each respective micro-operation that has i) an associated respective allow signal, ii) respective exception information indicating that the respective micro-operation will not generate an exception, and iii) no earlier respective micro-operations positioned earlier in the order that has respective exception information indicating that the earlier respective micro-operation will generate an exception, sending, by the VPU to the LSU, a respective commit signal associated with the respective micro-operation, wherein the LSU is configured to only execute a respective micro-operation upon receipt of a respective commit signal.
A processing system comprising a control unit, a vector processing unit (VPU) and a load-store unit (LSU), wherein:
- the control unit is configured to determine that there are no reasons internal to the control unit that are preventing a current instruction from making architectural updates, and in response send, to the VPU, an allow signal associated with the current instruction;
- the VPU is configured to send one or more respective micro-operations of the current instruction to the LSU in an order, and to send one or more respective allow signals associated with the respective micro-operation to the LSU;
- and
- the LSU is configured to determine, for each of a set of the one or more respective micro-operations having an associated respective allow signal, whether the respective micro-operation will generate a respective exception, and send respective exception information to the VPU, the respective exception information indicating whether the respective micro-operation will generate a respective exception;
- wherein the VPU is configured to send, for each respective micro-operation that has i) an associated respective allow signal, ii) respective exception information indicating that the respective micro-operation will not generate an exception, and iii) no earlier respective micro-operations positioned earlier in the order that has respective exception information indicating that the earlier respective micro-operation will generate an exception, a respective commit signal associated with the respective micro-operation to the LSU;
- and
- wherein the LSU is configured to only execute a respective micro-operation upon receipt of a respective commit signal associated with the respective micro-operation.
Dependencies are inferred from the claim text.