Method and apparatus for debugging an integrated circuit

A microprocessor having a normal mode for operation under normal operating conditions and a debug mode for operations to test and debug the microprocessor, comprising:

• a cache memory unit;
• a plurality of execution units;
• a plurality of output pins;
• a plurality of internal busses, wherein the plurality of execution units are interconnected through the plurality of internal busses;
• multiplexer circuitry having a first input coupled to the plurality of internal busses and a second input coupled the cache memory unit;
• and
• test control logic for setting the multiplexer in either the normal mode or the debug mode;
• wherein during the normal mode, external data requests resulting from misses in the cache memory unit are conveyed through the second input of the multiplexer circuitry to the output pins;
• and
• wherein during the debug mode, at least some signals of the plurality of internal busses are conveyed through the first input of the multiplexer circuitry to the output pins.