G06F 9/3806
Using address prediction
Official title: {using address prediction, e.g. return stack, branch history buffer}
G06F9/3806 (Using address prediction) appears on 1,215 US grants and 1,064 published applications in this corpus.
Search patents in G06F- Granted patents
- 1,215
- Published applications
- 1,064
- Assignees
- 220
- Inventors
- 1,644
- Latest grant
- 8 Sep 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1983 | 1 | 0 |
| 1984 | 0 | 0 |
| 1985 | 0 | 0 |
| 1986 | 3 | 0 |
| 1987 | 3 | 0 |
| 1988 | 1 | 0 |
| 1989 | 5 | 0 |
| 1990 | 3 | 0 |
| 1991 | 2 | 0 |
| 1992 | 7 | 0 |
| 1993 | 7 | 0 |
| 1994 | 11 | 0 |
| 1995 | 12 | 0 |
| 1996 | 17 | 0 |
| 1997 | 27 | 0 |
| 1998 | 48 | 0 |
| 1999 | 50 | 0 |
| 2000 | 46 | 0 |
| 2001 | 44 | 3 |
| 2002 | 22 | 23 |
| 2003 | 28 | 30 |
| 2004 | 17 | 39 |
| 2005 | 23 | 34 |
| 2006 | 24 | 34 |
| 2007 | 21 | 21 |
| 2008 | 24 | 44 |
| 2009 | 22 | 37 |
| 2010 | 28 | 31 |
| 2011 | 31 | 24 |
| 2012 | 19 | 29 |
| 2013 | 21 | 34 |
| 2014 | 33 | 52 |
| 2015 | 34 | 50 |
| 2016 | 69 | 48 |
| 2017 | 49 | 49 |
| 2018 | 28 | 42 |
| 2019 | 58 | 72 |
| 2020 | 77 | 80 |
| 2021 | 67 | 54 |
| 2022 | 61 | 47 |
| 2023 | 43 | 49 |
| 2024 | 49 | 37 |
| 2025 | 51 | 46 |
| 2026 | 29 | 55 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Device, method and system to capture or restore microarchitectural state of a processor core8 Sep 2026US 12,730,645 B2Intel Corporation
- Branch target buffer run-ahead8 Sep 2026US 12,730,646 B2Microsoft Technology Licensing, LLC
- Microprocessor that performs mid-fetch block restart abort processing28 Jul 2026US 12,693,864 B1Ventana Micro Systems Inc.
- Device for performing branch target buffer entry prefetching21 Jul 2026US 12,688,044 B2Microsoft Technology Licensing, LLC
- Concurrently fetching instructions for multiple decode clusters7 Jul 2026US 12,675,294 B2Intel Corporation
- Combined load value and load address prediction1 Oct 2026US 2026/0299955 A1
- Systems and methods for dynamically switching between branch prediction modes1 Oct 2026US 2026/0299956 A1Advanced Micro Devices, Inc.
- Branch target buffer run-ahead1 Oct 2026US 2026/0299957 A1Microsoft Technology Licensing, LLC
- Accelerated tage branch prediction with a tage cache10 Sep 2026US 2026/0267649 A1Akeana, Inc.
- Branch target buffer victim cache3 Sep 2026US 2026/0259735 A1Microsoft Technology Licensing, LLC
Most cited
By later US patents
- High performance superscalar microprocessor including a common reorder buffer and common register file for both integer and floating point operations320US 5,651,125 AAdvanced Micro Devices, Inc. · 1997
- System for reducing delay for execution subsequent to correctly predicted branch instruction using fetch information stored with each block of instructions in cache299US 5,136,697 AAdvanced Micro Devices, Inc. · 1992
- Method for pipeline processing of instructions by controlling access to a reorder buffer using a register file outside the reorder buffer215US 5,721,855 AIntel Corporation · 1998
- Branch prediction210US 5,142,634 ADigital Equipment Corporation · 1992
- Method and apparatus for performing reads of related data from a set-associative cache memory152US 5,802,602 AIntel Corporation · 1998