Branch target buffer victim cache
AssigneeMicrosoft Technology Licensing, LLC
InventorsJulio GAGO ALONSO, Santiago GALAN, Antonio JUAN HORMIGO, Ivan PIZARRO
Life of this patent
Estimating the term…
Abstract
Improved branch target buffer (BTB) structures are provided. A device can include branch target buffers storing entries corresponding to branch instructions and corresponding targets of the branch instructions. The device can include a victim cache storing a branch target buffer entry that has been evicted from a branch target buffer of the branch target buffers. The device can include branch prediction circuitry configured to access the victim cache responsive to receiving respective miss indications from each branch target buffer of the branch target buffers.
Claims20
A device comprising:
- branch target buffers storing entries corresponding to branch instructions and corresponding targets of the branch instructions;
- a victim cache storing a branch target buffer entry that has been evicted from a branch target buffer of the branch target buffers;
- branch prediction circuitry configured to access the victim cache responsive to receiving respective miss indications from each branch target buffer of the branch target buffers
- a miss queue coupled between the branch prediction circuitry and the victim cache, the miss queue configured to store a program counter value associated with an instruction of the instructions for which respective miss indications from each branch target buffer of the branch target buffers is received;
- and
- an eviction queue coupled between the branch target buffers and the victim cache, the eviction queue configured to receive the entry that has been evicted, wherein a write from the eviction queue has a lower priority than a read from the miss queue.
A method comprising:
- storing, by branch target buffers, entries corresponding to branch instructions and corresponding targets of the branch instructions;
- storing, by a victim cache, a branch target buffer entry that has been evicted from a branch target buffer of the branch target buffers;
- accessing, by branch prediction circuitry, the victim cache responsive to receiving respective miss indications from each branch target buffer of the branch target buffers
- storing, by a miss queue coupled between the branch prediction circuitry and the victim cache, a program counter value associated with an instruction of the instructions for which respective miss indications from each branch target buffer of the branch target buffers is received;
- and
- receiving, by an eviction queue coupled between the branch target buffers and the victim cache, the entry that has been evicted, wherein a write from the eviction queue has a lower priority than a read from the miss queue.
A non-transitory machine-readable medium including instructions that, when executed by a machine, cause the machine to perform operations comprising:
- storing, by branch target buffers, entries corresponding to branch instructions and corresponding targets of the branch instructions;
- storing, by a victim cache, a branch target buffer entry that has been evicted from a branch target buffer of the branch target buffers;
- accessing, by branch prediction circuitry, the victim cache responsive to receiving respective miss indications from each branch target buffer of the branch target buffers;
- storing, by a miss queue coupled between the branch prediction circuitry and the victim cache, a program counter value associated with an instruction of the instructions for which respective miss indications from each branch target buffer of the branch target buffers is received;
- and
- receiving, by an eviction queue coupled between the branch target buffers and the victim cache, the entry that has been evicted, wherein a write from the eviction queue has a lower priority than a read from the miss queue.
Dependencies are inferred from the claim text.