Concurrently fetching instructions for multiple decode clusters
AssigneeIntel Corporation
InventorsMathew Lowes, Martin Licht, Jonathan Combs
Life of this patent
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Abstract
In one embodiment, an apparatus comprises: a branch prediction circuit to predict whether a branch is to be taken; a fetch circuit, in a single fetch cycle, to send a first portion of a fetch region of instructions to a first decode cluster and send a second portion of the fetch region to the second decode cluster; the first decode cluster comprising a first plurality of decode circuits to decode one or more instructions in the first portion of the fetch region; and the second decode cluster comprising a second plurality of decode circuits to decode one or more other instructions in the second portion of the fetch region. Other embodiments are described and claimed.
Claims14
An apparatus comprising:
- a branch prediction circuit to predict whether a branch is to be taken;
- a fetch circuit coupled to the branch prediction circuit, wherein the fetch circuit, in a single fetch cycle, is to send a first portion of a fetch region of instructions to a first decode cluster and send a second portion of the fetch region to a second decode cluster when the fetch region comprises multiple predictions;
- the first decode cluster coupled to the fetch circuit, the first decode cluster comprising a first plurality of decode circuits to decode one or more instructions in the first portion of the fetch region;
- and
- the second decode cluster coupled to the fetch circuit, the second decode cluster comprising a second plurality of decode circuits to decode one or more other instructions in the second portion of the fetch region.
A processor comprising:
- a branch prediction circuit to identify a first branch and a second branch within a fetch region of code, wherein when the fetch region comprises a target of the first branch, the branch prediction circuit is to identify a double prediction in the fetch region;
- a fetch circuit coupled to the branch prediction circuit, wherein in response to the double prediction identification, the fetch circuit, in a single fetch cycle, is to send a first portion of the fetch region to a first decode cluster and send a second portion of the fetch region to a second decode cluster;
- the first decode cluster coupled to the fetch circuit, the first decode cluster comprising a first plurality of decode circuits to decode one or more instructions in the first portion of the fetch region;
- and
- the second decode cluster coupled to the fetch circuit, the second decode cluster comprising a second plurality of decode circuits to decode one or more other instructions in the second portion of the fetch region concurrently with the first decode cluster decoding of the one or more instructions in the first portion of the fetch region.
Dependencies are inferred from the claim text.