Combined load value and load address prediction
OwnerSudhanshu SHUKLA, Jayesh GAUR +3inventors
InventorsSudhanshu SHUKLA, Jayesh GAUR, Raphael ZAILER, Chen DAN, Sreenivas SUBRAMONEY
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Abstract
A processor of an aspect includes a decode unit to decode a load instruction. The load instruction is to indicate a destination register. The processor also includes a prediction unit to provide either a predicted address or a predicted value for the load instruction. The processor also includes a memory execution unit coupled with the prediction unit. The memory execution unit is to load a value corresponding to the predicted address and store the loaded value in the destination register or store the predicted value in the destination register. Other processors, methods, and systems are also disclosed.
Claims20
A processor comprising:
- a decode unit to decode a load instruction, the load instruction to indicate a destination register;
- a prediction unit to provide either a predicted address or a predicted value for the load instruction;
- and
- a memory execution unit coupled with the prediction unit, the memory execution unit to:
- load a value corresponding to the predicted address and store the loaded value in the destination register;
- or
- store the predicted value in the destination register.
A method comprising:
- decoding a load instruction, the load instruction indicating a destination register;
- predicting either a predicted address or a predicted value for the load instruction;
- and
- loading a value corresponding to the predicted address and storing the loaded value in the destination register, in the case of predicting the predicted address;
- or
- storing the predicted value in the destination register, in the case of predicting the predicted value.
A system comprising:
- a processor comprising:
- a decode unit to decode a load instruction, the load instruction to indicate a destination register;
- a prediction unit to provide either a predicted address or a predicted value for the load instruction;
- and
- a memory execution unit coupled with the prediction unit, the memory execution unit to:
- load a value corresponding to the predicted address and store the loaded value in the destination register;
- or
- store the predicted value in the destination register;
- and
- a dynamic random access memory (DRAM) coupled with the processor.
Dependencies are inferred from the claim text.