US 12,693,864 B1Granted

Microprocessor that performs mid-fetch block restart abort processing

AssigneeVentana Micro Systems Inc.

InventorsJohn G. Favor, Michael N. Michael, David S. Oliver

Life of this patent

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Abstract

A microprocessor prediction circuit performs a first lookup of a fetch block start address (FBSA) in a fetch block predictor, detects a hit on a fetch block (FBlk), and generates a first FBlk descriptor (FBD). An instruction fetch circuit uses the first FBD to fetch the FBlk from an instruction cache. A control circuit receives an abort request associated with an instruction of the FBlk, determines an abort point separating the FBlk into former and latter portions, flushes the latter portion, allows the former portion to execute, and provides the abort point to the prediction circuit. The prediction circuit performs a second FBSA lookup, detects a hit on the same entry, and generates a second FBD describing at least the latter portion. The instruction fetch circuit uses the second FBD to re-fetch at least the latter portion, which the microprocessor executes, but does not re-execute the former portion.

Claims23

Dependent claims

A microprocessor, comprising:

an instruction cache;
a prediction circuit configured to:
perform a first lookup of a fetch block start address (FBSA) in a fetch block predictor (FBP);
detect that the FBSA hits on an entry of the FBP that predicts a fetch block (FBlk) of architectural instructions is present in a program instruction stream, wherein the FBlk comprises a sequential run of architectural instructions;
and
use the hit entry to generate a first FBlk descriptor (FBD) that describes the FBlk;
an instruction fetch circuit configured to use the first FBD to fetch the architectural instructions of the FBlk from the instruction cache for execution;
and
a control circuit configured to:
receive from an execution circuit an abort request that indicates an architectural instruction of the FBlk caused a need for an abort;
determine, in response to the abort request, an abort point that separates the FBlk into a former portion and a latter portion;
flush the latter portion of the FBlk;
allow the former portion of the FBlk to execute;
and
provide the abort point to the prediction circuit and signal the prediction circuit to restart at the FBSA of the FBlk;
wherein the prediction circuit is further configured to, in response to the signal:
perform a second lookup of the FBSA of the FBlk in the FBP;
detect that the FBSA hits on the same entry of the FBP that predicts the FBlk is present in the program instruction stream;
and
use the hit entry to generate a second FBD that describes at least the latter portion of the FBlk;
wherein the instruction fetch circuit is further configured to use the second FBD to fetch at least the latter portion of the FBlk from the instruction cache for execution;
and
wherein the microprocessor executes the latter portion of the FBlk but does not re-execute the former portion of the FBlk.

20 more elements

A method, comprising:

in a microprocessor comprising:
an instruction cache;
a prediction circuit;
an instruction fetch circuit;
and
a control circuit;
by the prediction circuit:
performing a first lookup of a fetch block start address (FBSA) in a fetch block predictor (FBP);
detecting that the FBSA hits on an entry of the FBP that predicts a fetch block (FBlk) of architectural instructions is present in a program instruction stream, wherein the FBlk comprises a sequential run of architectural instructions;
and
using the hit entry to generate a first FBlk descriptor (FBD) that describes the FBlk;
using, by the instruction fetch circuit, the first FBD to fetch the architectural instructions of the FBlk from the instruction cache for execution;
and
by the control circuit:
receiving from an execution circuit an abort request that indicates an architectural instruction of the FBlk caused a need for an abort;
determining, in response to the abort request, an abort point that separates the FBlk into a former portion and a latter portion;
flushing the latter portion of the FBlk;
allowing the former portion of the FBlk to execute;
and
providing the abort point to the prediction circuit and signaling the prediction circuit to restart at the FBSA of the FBlk;
by the prediction circuit in response to the signal:
performing a second lookup of the FBSA of the FBlk in the FBP;
detecting that the FBSA hits on the same entry of the FBP that predicts the FBlk is present in the program instruction stream;
and
using the hit entry to generate a second FBD that describes at least the latter portion of the FBlk;
using, by the instruction fetch circuit, the second FBD to fetch at least the latter portion of the FBlk from the instruction cache for execution;
and
executing, by the microprocessor, the latter portion of the FBlk but not re-executing the former portion of the FBlk.

25 more elements

A non-transitory computer-readable medium having instructions stored thereon that are capable of configuring a microprocessor, wherein the instructions configure the microprocessor to perform a method comprising:

in a microprocessor comprising:
an instruction cache;
a prediction circuit;
an instruction fetch circuit;
and
a control circuit;
by the prediction circuit:
performing a first lookup of a fetch block start address (FBSA) in a fetch block predictor (FBP);
detecting that the FBSA hits on an entry of the FBP that predicts a fetch block (FBlk) of architectural instructions is present in a program instruction stream, wherein the FBlk comprises a sequential run of architectural instructions;
and
using the hit entry to generate a first FBlk descriptor (FBD) that describes the FBlk;
using, by the instruction fetch circuit, the first FBD to fetch the architectural instructions of the FBlk from the instruction cache for execution;
and
by the control circuit:
receiving from an execution circuit an abort request that indicates an architectural instruction of the FBlk caused a need for an abort;
determining, in response to the abort request, an abort point that separates the FBlk into a former portion and a latter portion;
flushing the latter portion of the FBlk;
allowing the former portion of the FBlk to execute;
and
providing the abort point to the prediction circuit and signaling the prediction circuit to restart at the FBSA of the FBlk;
by the prediction circuit in response to the signal:
performing a second lookup of the FBSA of the FBlk in the FBP;
detecting that the FBSA hits on the same entry of the FBP that predicts the FBlk is present in the program instruction stream;
and
using the hit entry to generate a second FBD that describes at least the latter portion of the FBlk;
using, by the instruction fetch circuit, the second FBD to fetch at least the latter portion of the FBlk from the instruction cache for execution;
and
executing, by the microprocessor, the latter portion of the FBlk but not re-executing the former portion of the FBlk.

25 more elements

Dependencies are inferred from the claim text.

Facts

Application: 18/813,201Filed 23 Aug 2024 · continuation in part
Priority: 30 Aug 2023
Granted: 28 Jul 2026
Term ends: Not estimatedThe source records don’t support an estimate.

Classification8 codes

G06F 9/30065
To perform operations for flow control: loop control instructions; iterative instructions, e.g. LOOP, REPEAT
G06F 9/3806
For branches, e.g. hedging, branch folding: using address prediction, e.g. return stack, branch history buffer
G06F 9/30181
Arrangements for executing machine instructions, e.g. instruction decode: instruction operation extension or modification
G06F 9/3802
Concurrent instruction execution, e.g. pipeline or look ahead: instruction prefetching

Family

Application18/240,249Parent of this continuation-in-part · filed 30 Aug 2023
Application18/380,150Parent of this continuation-in-part · filed 13 Oct 2023
Application18/380,152Parent of this continuation-in-part · filed 13 Oct 2023
Application63/547,230Us provisional application · filed 3 Nov 2023
Application18/645,260Parent of this continuation-in-part · filed 24 Apr 2024
Application18/645,249Parent of this continuation-in-part · filed 24 Apr 2024
Application18/645,269Parent of this continuation-in-part · filed 24 Apr 2024
Application18/645,239Parent of this continuation-in-part · filed 24 Apr 2024
Application18/645,272Parent of this continuation-in-part · filed 24 Apr 2024
Application18/645,281Parent of this continuation-in-part · filed 24 Apr 2024
Application18/645,274Parent of this continuation-in-part · filed 24 Apr 2024
US 12,498,926 B1Parent of this continuation-in-part
US 12,450,066 B1Parent of this continuation-in-part
US 12,493,469 B1Parent of this continuation-in-part
US 12,450,067 B1Parent of this continuation-in-part
US 12,493,466 B1Parent of this continuation-in-part
US 12,498,927 B1Parent of this continuation-in-part
US 12,498,928 B1Parent of this continuation-in-part
US 12,299,449 B1Parent of this continuation-in-part
US 12,282,430 B1Parent of this continuation-in-part
US 12,253,951 B1Parent of this continuation-in-part
US 12,216,583 B1Related patent
US 2025/0077438 A1Published application
US 12,693,864 B1This patent

From the US filing history. Foreign family members aren’t listed.