Method for pipeline processing of instructions by controlling access to a reorder buffer using a register file outside the reorder buffer

A pipelined method for executing a plurality of instructions in a computer system, said method comprising the steps of:

• decoding the plurality of instructions in order to produce a plurality of operations, wherein the step of decoding includes the steps of
• maintaining a readiness indication of source data for the plurality of operations in a storage area outside a reorder buffer in an in-order processing portion of a processor;
• writing the plurality of operations into a reservation station in an out-of-order execution core of the processor at the same time and
• reading data from the reorder buffer for use in execution of the plurality of operations, simultaneously to writing the plurality of operations into the reservation station, only if data is indicated as ready in the storage area;
• executing the plurality of operations with at least one of the plurality of operations being executed out-of-order, wherein the step of executing includes the steps of
• scheduling and dispatching individual operations as data required for execution of each of the individual operations is ready,
• executing each of said individual operations, and
• writing back results from execution including associatively writing at least one result to the reservation station,
• wherein the steps of scheduling and dispatching, executing and writing back are performed in consecutive pipestages;
• and
• committing results from execution of the plurality of operations to architectural state in order of issuance of the plurality of operations.

A method for executing a plurality of instructions in a computer system, said method comprising the steps of:

• providing the plurality of instructions as a plurality of operations in an in-order pipeline, wherein the step of providing the plurality of instructions includes the steps of
• performing an instruction cache memory lookup to fetch the plurality of instructions,
• performing instruction length decoding,
• rotating the plurality of instructions, and
• decoding the plurality of instructions in an instruction decoder to generate the plurality of operations,
• performing register renaming, allocating resources and maintaining a readiness indication of source data for the plurality of operations in a storage area outside a reorder buffer, issuing the plurality of operations including the steps sending a portion of each of the plurality of operations to a reservation station at the same time and reading source data from the reorder buffer if valid as indicated in the storage area,
• wherein the steps of performing an instruction cache memory lookup, performing instruction length decoding, rotating the plurality of instructions, decoding the plurality of instructions, and performing register renaming are performed in consecutive pipestages;
• executing the plurality of operations in an out-of-order pipeline to produce execution results, wherein the step of executing includes the steps of
• determining execution readiness of each of the plurality of operations and scheduling individual operations in the plurality of operations that have source data available,
• dispatching individual operations to an execution unit as data required for each said individual operation is ready,
• executing said individual operations and writing back the results, including associatively writing at least one result to the reservation station,
• wherein the steps of determining execution readiness, dispatching and executing are performed in consecutive pipestages;
• and
• retiring each of the plurality of operations, wherein results from execution are committed to architectural state and order is reestablished.

A pipeline method for executing a plurality of instructions in a computer system, said method comprising the steps of:

• decoding the plurality of instructions in order into a plurality of micro-operations;
• writing the plurality of operations into a reservation station at the same time;
• reading source data, simultaneously to the step of writing the plurality of micro-operations into a reservation station, from a reorder buffer only if indicated as ready in a register file outside the reorder buffer;
• executing the plurality of micro-operations with at least one of the plurality of micro-operations being executed out-of-order;
• writing back results from execution of the plurality of operations including associatively writing at least one result to the reservation station;
• committing results from execution of the plurality of operations to the out-of-order execution core.