G06F 9/3804
For branches
Official title: {for branches, e.g. hedging, branch folding}
G06F9/3804 (For branches) appears on 1,773 US grants and 1,437 published applications in this corpus.
Search patents in G06F- Granted patents
- 1,773
- Published applications
- 1,437
- Assignees
- 304
- Inventors
- 2,309
- Latest grant
- 22 Sep 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1978 | 1 | 0 |
| 1979 | 0 | 0 |
| 1980 | 2 | 0 |
| 1981 | 0 | 0 |
| 1982 | 1 | 0 |
| 1983 | 1 | 0 |
| 1984 | 1 | 0 |
| 1985 | 1 | 0 |
| 1986 | 4 | 0 |
| 1987 | 4 | 0 |
| 1988 | 8 | 0 |
| 1989 | 10 | 0 |
| 1990 | 8 | 0 |
| 1991 | 7 | 0 |
| 1992 | 20 | 0 |
| 1993 | 23 | 0 |
| 1994 | 17 | 0 |
| 1995 | 28 | 0 |
| 1996 | 33 | 0 |
| 1997 | 46 | 0 |
| 1998 | 83 | 0 |
| 1999 | 70 | 0 |
| 2000 | 77 | 0 |
| 2001 | 73 | 10 |
| 2002 | 45 | 39 |
| 2003 | 41 | 45 |
| 2004 | 29 | 52 |
| 2005 | 30 | 47 |
| 2006 | 36 | 51 |
| 2007 | 30 | 38 |
| 2008 | 34 | 62 |
| 2009 | 40 | 52 |
| 2010 | 43 | 38 |
| 2011 | 40 | 30 |
| 2012 | 28 | 45 |
| 2013 | 29 | 45 |
| 2014 | 44 | 66 |
| 2015 | 39 | 63 |
| 2016 | 83 | 69 |
| 2017 | 68 | 89 |
| 2018 | 41 | 51 |
| 2019 | 75 | 85 |
| 2020 | 96 | 97 |
| 2021 | 87 | 76 |
| 2022 | 78 | 62 |
| 2023 | 59 | 59 |
| 2024 | 62 | 43 |
| 2025 | 63 | 59 |
| 2026 | 35 | 64 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Subgroups
Granted patents
Recent patents
- Instruction fetching22 Sep 2026US 12,743,281 B2Arm Limited
- Device, method and system to capture or restore microarchitectural state of a processor core8 Sep 2026US 12,730,645 B2Intel Corporation
- Branch target buffer run-ahead8 Sep 2026US 12,730,646 B2Microsoft Technology Licensing, LLC
- Microprocessor that performs mid-fetch block restart abort processing28 Jul 2026US 12,693,864 B1Ventana Micro Systems Inc.
- Device for performing branch target buffer entry prefetching21 Jul 2026US 12,688,044 B2Microsoft Technology Licensing, LLC
- Combined load value and load address prediction1 Oct 2026US 2026/0299955 A1
- Systems and methods for dynamically switching between branch prediction modes1 Oct 2026US 2026/0299956 A1Advanced Micro Devices, Inc.
- Branch target buffer run-ahead1 Oct 2026US 2026/0299957 A1Microsoft Technology Licensing, LLC
- Accelerated tage branch prediction with a tage cache10 Sep 2026US 2026/0267649 A1Akeana, Inc.
- Branch target buffer victim cache3 Sep 2026US 2026/0259735 A1Microsoft Technology Licensing, LLC
Most cited
By later US patents
- System and method for controlling a highly parallel multiprocessor using an anarchy based scheduler for parallel execution thread scheduling448US 5,179,702 ASupercomputer Systems Limited Partnership · 1993
- Apparatus and method for aborting un-needed instruction fetches in a digital microprocessor device433US 6,092,186 ALucent Technologies Inc. · 2000
- Processor having plurality of functional units for orderly retiring outstanding operations based upon its associated tags403US 5,226,126 ANexgen Microsystems · 1993
- Method and apparatus for user side scheduling in a multiprocessor operating system program that implements distributive scheduling of processes323US 6,195,676 B1Silicon Graphics, Inc. · 2001
- High performance superscalar microprocessor including a common reorder buffer and common register file for both integer and floating point operations320US 5,651,125 AAdvanced Micro Devices, Inc. · 1997