Apparatus and method for aborting un-needed instruction fetches in a digital microprocessor device

A digital processor device for use in a digital data processing system having external memory elements that operates synchronously with respect to a periodic clock signal, wherein access time to said external memory elements is substantially slower than access times to internal memory elements of said digital processor, said processor comprising:

• a fetch unit for performing instruction fetches requested from a decode unit of said digital processor to said external memory elements in a given number of clock periods, said fetch unit having a fetch program counter for storing addresses of said instruction fetches;
• and
• a decode unit coupled to said fetch unit for decoding instructions received therein as a result of said instruction fetches, wherein said decode unit is operable to generate a "jump taken" signal to said fetch unit when a discontinuity is to occur in a given instruction fetch sequence, said jump taken signal indicative that fetching is to resume at a new value of said fetch program counter, thereby causing any prefetched ones of said instruction fetches to be discarded;
• and
• wherein said decode element further includes a memory controller coupled to said fetch unit for performing fetch requests at given locations in said external memory elements, wherein said fetch unit is operable to generate an "abort" signal to said memory controller upon receipt of said jump taken signal if said memory controller has initiated an outstanding memory request, whereby said outstanding memory request is terminated in fewer than said given number of clock periods in response to said abort signal.

A method of operating a digital processor in order to eliminate un-needed instruction fetches, said method comprising the steps of:

• transmitting instruction fetches requested by a decode unit of said digital processor from a fetch unit thereof to a memory controller;
• performing fetch requests at given locations in a memory element external to said digital processor by means of said memory controller in a given number of clock periods;
• decoding instructions received at said decode unit as a result of said instruction fetches;
• generating a "jump taken" signal to said fetch unit of said digital processor when a discontinuity is to occur in a given instruction fetch sequence;
• and
• generating an "abort" signal to said memory controller upon receipt of said jump taken signal if said memory controller has initiated an outstanding memory request, whereby said outstanding memory request is terminated in fewer than said given number of clock periods in response to said abort signal.