Method and apparatus for performing reads of related data from a set-associative cache memory
AssigneeIntel Corporation
InventorsMonis Rahman, Mircea Poplingher, Tse-Yu Yeh, Wenliang Chen
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AssigneeIntel Corporation
InventorsMonis Rahman, Mircea Poplingher, Tse-Yu Yeh, Wenliang Chen
Estimating the term…
Allocation circuitry for allocating entries within a set-associative cache memory is disclosed. The set-associative cache memory comprises N ways, each way having M entries and corresponding entries in each of the N ways constituting a set of entries. The allocation circuitry has a first circuit which identifies related data units by identifying a probability that the related data units may be successively read from the cache memory. A second circuit within the allocation circuitry allocates the corresponding entries in each of the ways to the related data units, so that related data units are stored in a common set of entries. Accordingly, the related data units will be simultaneously outputted from the set-associative cache memory, and are thus concurrently available for processing. The invention may find application in allocating entries of a common set in a branch prediction table (BPT) to branch prediction information for related branch instructions.
A computer-implemented method of allocating entries within a set-associative cache memory having first and second ways, each way having a plurality of entries, wherein corresponding entries of each of the first and second ways comprise respective sets of entries, the method comprising the steps of:
A computer-implement method of accessing a set-associative cache memory including first and second ways, wherein each of the first and second ways has first and second entries and wherein the respective first entries together comprise a first set and the respective second entries together comprise a second set, the method comprising the steps of:
A computer-implement method of allocating information units to, and retrieving information units from, a set-associative memory cache including X ways, wherein each of the X ways has Y entries and wherein corresponding entries in each of the X ways comprise a set, the method comprising the steps of:
Allocation circuitry for allocating entries within a set-associative cache memory, the set-associative cache memory comprising first and second ways, each way having first and second entries, the first entries of the respective first and second ways comprising a first set, and the second entries of the respective first and second ways comprising a second set, the allocation circuitry comprising:
A set-associative cache memory arrangement comprising:
Apparatus for allocating entries within a set-associative cache memory, the set-associative cache memory comprising first and second ways, each way having first and second entries, the first entries of the respective first and second ways comprising a first set, and the second entries of the respective first and second ways comprising a second set, the apparatus comprising:
Dependencies are inferred from the claim text.