G06F 30/347
Physical level
Official title: Physical level, e.g. placement or routing
G06F30/347 (Physical level) appears on 664 US grants and 473 published applications in this corpus.
Search patents in G06F- Granted patents
- 664
- Published applications
- 473
- Assignees
- 166
- Inventors
- 1,225
- Latest grant
- 22 Sep 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1991 | 1 | 0 |
| 1992 | 0 | 0 |
| 1993 | 0 | 0 |
| 1994 | 0 | 0 |
| 1995 | 4 | 0 |
| 1996 | 1 | 0 |
| 1997 | 4 | 0 |
| 1998 | 8 | 0 |
| 1999 | 4 | 0 |
| 2000 | 7 | 0 |
| 2001 | 9 | 1 |
| 2002 | 8 | 2 |
| 2003 | 7 | 6 |
| 2004 | 6 | 8 |
| 2005 | 9 | 8 |
| 2006 | 15 | 9 |
| 2007 | 23 | 9 |
| 2008 | 9 | 7 |
| 2009 | 16 | 6 |
| 2010 | 15 | 8 |
| 2011 | 18 | 11 |
| 2012 | 27 | 14 |
| 2013 | 25 | 13 |
| 2014 | 48 | 16 |
| 2015 | 34 | 24 |
| 2016 | 40 | 29 |
| 2017 | 34 | 25 |
| 2018 | 38 | 40 |
| 2019 | 56 | 25 |
| 2020 | 36 | 26 |
| 2021 | 25 | 30 |
| 2022 | 36 | 39 |
| 2023 | 33 | 37 |
| 2024 | 31 | 37 |
| 2025 | 20 | 17 |
| 2026 | 17 | 26 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Balancing buffer insertion for clock H-trees22 Sep 2026US 12,743,573 B1Cadence Design Systems, Inc.
- Dynamic power load line by configuration15 Sep 2026US 12,737,521 B2Altera Corporation
- Systems and methods for programmable fabric design compilation28 Jul 2026US 12,694,180 B2Altera Corporation
- Hardware redaction via designer-directed fine-grained embedded field programmable gate array insertion7 Jul 2026US 12,675,626 B1Carnegie Mellon University
- Programmable sequence-driven hardware trigger for multiple FPGA system30 Jun 2026US 12,670,307 B1Cadence Design Systems, Inc.
- Method for Computing a Circuit Simulation with Respect to a Driver3 Sep 2026US 2026/0260049 A1Microchip Technology Incorporated
- Edge-weighted graph neural networks for post-placement interconnect capacitance estimation of analog circuits13 Aug 2026US 2026/0236653 A1Drexel University
- System and method for predicting power consumption of integrated circuit and method for designing integrated circuit using the same9 Jul 2026US 2026/0195514 A1SK hynix Inc.
- Programmable Logic Device Embedded Block Power Control2 Jul 2026US 2026/0187331 A1Altera Corporation
- Parallel routing method for two-stage partitions using genetic algorithm25 Jun 2026US 2026/0178811 A1ASICLAND Co., Ltd.
Most cited
By later US patents
- Method of using electronically reconfigurable logic circuits320US 5,036,473 AMentor Graphics Corporation · 1991
- Method of removing gated clocks from the clock nets of a netlist for timing sensitive implementation of the netlist in a hardware emulation system311US 5,452,239 AQuickturn Design Systems, Inc. · 1995
- Work group computing for electronic design automation309US 5,983,277 AAltera Corporation · 1999
- Tileable field-programmable gate array architecture261US 6,888,375 B2Actel Corporation · 2005
- Graphic editor for block diagram level design of circuits212US 6,110,223 AAltera Corporation · 2000