US 12,670,307 B1 · Programmable sequence-driven hardware trigger for multiple FPGA system

Abstract

Disclosed herein are systems and methods of a prototyping system for circuit design testing. The prototyping system employs hardware (“Debug FPGA”) that performs a series of Boolean evaluations according to testbench configurations loaded at runtime. FPGAs performing the DUT operate synchronously, in which each component must start, stop, and step through the DUT's operations according to the Boolean operations of the Debug FPGA. The hardware and software functions disclosed simultaneously stop the clocks of the FPGAs according to user-defined trigger conditions in the DUT output, allowing the designer to stop the prototyping system to analyze or debug the DUT. Based on the data outputs from the FPGAs performing the DUT, the Boolean expressions of the Debug FPGA detect state transitions or trigger events occurring within the DUT. When the Debug FPGA detects a trigger event, the Debug FPGA transmits a clock-stopping signal to each of the FPGAs.

Claims20

Dependent claims

A system for prototyping designs-under-test (DUTs) of integrated circuit (IC) designs using programmable field-programmable gate arrays (FPGAs), the system comprising:

a debug FPGA configured to:
receive a signal pattern of data received from one or more user FPGAs performing a DUT;
identify a state transition of the DUT based upon the signal pattern from the one or more user FPGAs performing the DUT;
identify a trigger event based upon comparing the signal pattern against a trigger condition stored into a trigger mask register of the debug FPGA that is updated for each clock cycle, wherein the trigger condition is based on machine-executable testbench instructions of a configuration file;
and
transmit a trigger signal to the one or more user FPGAs for stopping a clock of the one or more user FPGAs in response to identifying the trigger event.

3 more elements

A system for prototyping designs-under-test (DUTs) of integrated circuit (IC) designs using programmable field-programmable gate arrays (FPGAs), the system comprising:

a plurality of user FPGAs, including a set of one or more user FPGAs configured to:
receive an instruction set for performing a DUT for an IC design file;
and
generate a data output based upon the instruction set for a clock cycle of a clock associated with the set of one or more user FPGAs;
and
a debug FPGA configured to:
identify a trigger event based upon comparing a signal pattern for each data output from the set of one or more user FPGAs against a trigger condition stored into a trigger mask register of the debug FPGA that is updated for each clock cycle, wherein the trigger condition is based on machine-executable testbench instructions of a configuration file;
identify a master FPGA of the set of one or more user FPGAs based upon a destination indicator of a master mask register;
and
transmit a trigger signal to the master FPGA of the set of one or more user FPGAs for stopping the clock at the master FPGA for the set of one or more user FPGAs.

7 more elements

A system for prototyping designs-under-test (DUTs) of integrated circuit (IC) designs using programmable field-programmable gate arrays (FPGAs), the system comprising:

a processor configured to:
compile a plurality of instruction sets for a DUT from an IC design file and a plurality of testbench instructions according to one or more configuration files;
and
for a first clock cycle of the DUT, parse the plurality of testbench instructions for a plurality of registers of a debug FPGA;
and
the debug FPGA configured to, for the first clock cycle of the DUT:
update the plurality of registers according to the plurality of testbench instructions parsed for the first clock cycle, including a trigger mask register;
identify a trigger event based upon comparing a signal pattern for data outputs from one or more user FPGAs against a trigger condition indicated by the trigger mask register, wherein the trigger condition is based on the plurality of testbench instructions of the one or more configuration files;
and
transmit a trigger signal to the one or more user FPGAs for stopping a clock of the one or more user FPGAs in response to identifying the trigger event.

7 more elements

Dependencies are inferred from the claim text.

Programmable sequence-driven hardware trigger for multiple FPGA system

Life of this patent

Programmable sequence-driven hardware trigger for multiple FPGA system

Life of this patent

Abstract

Claims20