US 12,675,626 B1Granted

Hardware redaction via designer-directed fine-grained embedded field programmable gate array insertion

AssigneeCarnegie Mellon University

InventorsKenneth W. Mai, Prashanth Mohan, Ahmet Atli, Ogun Onur Kibar

Life of this patent

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Abstract

Disclosed herein is a system and method for using reconfigurable logic for hardware redaction in which the critical IP is obfuscated by replacing it with an eFPGA, thereby entirely concealing the logic and interconnects from reverse engineers and untrusted fabrication facilities. The non-critical intellectual property of the hardware is left unaltered such that the overall VLSI overheads (e.g., area, power, and performance) can be kept to a minimum.

Claims16

Dependent claims

A method for hardware-based redaction of a circuit to obscure redacted portions of the circuit comprising:

receiving an indication of one or more portions of the circuit to be redacted;
determining, for each redacted portion of the circuit, a smallest eFPGA fabric required to map the redacted portion onto an eFPGA;
generating the smallest eFPGA fabric for each of the one or more portions of the circuit to be redacted;
replacing, in a soft design of the circuit, each of the one or more redacted portions of the circuit with the eFPGA fabric generated for that redacted portion to create a mixed ASIC/eFPGA design;
performing a logic synthesis and timing analysis of the mixed ASIC/eFPGA design;
and
generating a layout of the redacted circuit, including the eFPGA fabrics generated for each of the redacted portions based on the mixed ASIC/eFPGA design.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/870,994Filed 22 Jul 2022 · us provisional application
Priority: 22 Jul 2021
Granted: 7 Jul 2026
Term ends: Not estimatedThe source records don’t support an estimate.

Classification8 codes

G06F 30/347
For reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]: physical level, e.g. placement or routing
G06F 30/3315
Design verification, e.g. functional simulation or model checking: using static timing analysis [STA]
G06F 30/337
Circuit design at the digital level: design optimisation
G06F 30/34
Circuit design: for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]

Family

Application63/224,459Us provisional application · filed 22 Jul 2021
US 12,675,626 B1This patent

From the US filing history. Foreign family members aren’t listed.

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Abstract

Facts

Application

17/870,994Filed 22 Jul 2022 · us provisional application

Priority

22 Jul 2021

Granted

7 Jul 2026

Term ends

Not estimatedThe source records don’t support an estimate.

Classification8 codes

G06F 30/347
For reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]: physical level, e.g. placement or routing
G06F 30/3315
Design verification, e.g. functional simulation or model checking: using static timing analysis [STA]
G06F 30/337
Circuit design at the digital level: design optimisation
G06F 30/34
Circuit design: for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]