G06F 2113/18
Chip packaging
G06F2113/18 (Chip packaging) appears on 282 US grants and 295 published applications in this corpus.
Search patents in G06F- Granted patents
- 282
- Published applications
- 295
- Assignees
- 138
- Inventors
- 861
- Latest grant
- 25 Aug 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1992 | 1 | 0 |
| 1993 | 1 | 0 |
| 1994 | 1 | 0 |
| 1995 | 0 | 0 |
| 1996 | 2 | 0 |
| 1997 | 4 | 0 |
| 1998 | 0 | 0 |
| 1999 | 0 | 0 |
| 2000 | 1 | 0 |
| 2001 | 4 | 1 |
| 2002 | 0 | 4 |
| 2003 | 9 | 7 |
| 2004 | 4 | 6 |
| 2005 | 3 | 6 |
| 2006 | 8 | 3 |
| 2007 | 3 | 6 |
| 2008 | 4 | 9 |
| 2009 | 9 | 16 |
| 2010 | 6 | 13 |
| 2011 | 9 | 6 |
| 2012 | 19 | 9 |
| 2013 | 16 | 16 |
| 2014 | 22 | 12 |
| 2015 | 11 | 14 |
| 2016 | 15 | 11 |
| 2017 | 9 | 8 |
| 2018 | 10 | 7 |
| 2019 | 13 | 20 |
| 2020 | 28 | 12 |
| 2021 | 22 | 14 |
| 2022 | 9 | 17 |
| 2023 | 10 | 21 |
| 2024 | 11 | 16 |
| 2025 | 11 | 22 |
| 2026 | 7 | 19 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Systems and methods for automatically generating a printed circuit board design25 Aug 2026US 12,717,990 B2Advanced Micro Devices, Inc.
- Multiscale thermal reduced order model for transient IC analysis28 Jul 2026US 12,694,183 B1Ansys, Inc.
- Evaluation apparatus, evaluation method, and evaluation program26 May 2026US 12,639,485 B2Tokyo Electron Limited
- Nanofabrication and design techniques for 3D ICs and configurable ASICs19 May 2026US 12,632,634 B2Board of Regents, The University of Texas System
- Nanofabrication and design techniques for 3D ICs and configurable ASICs7 Apr 2026US 12,596,863 B2Board of Regents, The University of Texas System
- System and Method for Simulating Underfill Flow during Packaging of Chip Assembly27 Aug 2026US 2026/0252771 A1Coretech System Co., Ltd.
- Reliability assessment of an electronic component carrier or a package comprising it using ai-supported finite elements analysis20 Aug 2026US 2026/0244825 A1AT&S Austria Technologie & Systemtechnik Aktiengesellschaft
- Modularization for data collection for large data models in advanced packaging interconnects20 Aug 2026US 2026/0244839 A1
- Generating load-balanced multi-cluster network on chip6 Aug 2026US 2026/0228389 A1Baya Systems, Inc.
- Nanofabrication and design techniques for 3d ics and configurable asics30 Jul 2026US 2026/0220344 A1Board of Regents, The University of Texas System
Most cited
By later US patents
- Asymmetric mesh NoC topologies93US 8,601,423 B1NetSpeed Systems · 2013
- System and method for across-chip thermal and power management in stacked IC designs72US 8,701,073 B1Taiwan Semiconductor Manufacturing Company.Ltd · 2014
- 2.5D electronic package69US 9,583,431 B1Altera Corporation · 2017
- Layout design system providing extended active area in filler design and semiconductor device fabricated using the system65US 9,514,260 B2Samsung Electronics Co., Ltd. · 2016
- Asymmetric mesh NoC topologies58US 8,819,611 B2NetSpeed Systems · 2014