Layout design system providing extended active area in filler design and semiconductor device fabricated using the system
AssigneeSamsung Electronics Co., Ltd.
InventorJin-Tae Kim
Life of this patent
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Abstract
A layout design system includes a storage unit storing first and second standard cell designs, and a displacement module that arranges the first and second standard cell designs to generate an intermediate design in accordance with the chip design requirement. A first area for the first standard cell design and a second area for the second standard cell design are separated in the intermediate design by a filler design having no active area. Extended active areas are formed in the filler design in relation to the first standard cell design and second standard cell design.
Claims19
A layout design system that receives a chip design requirement and provides a corresponding chip design to a circuit that stores the chip design, the layout design system comprising:
- a processor;
- a storage unit that stores a first standard cell design defining a first active area having a first width and a second standard cell design defining a second active area having a second width different from the first width;
- and
- a displacement module operating in conjunction with the processor and configured to;
- arrange the first standard cell design in a first area and the second standard cell in a second area to generate an intermediate design in accordance with the chip design requirement, wherein the first area and the second area are separated in the intermediate design by a filler design having no active area,
- generate a first marker corresponding to the first width at a first boundary between the filler design and the first area and a second marker corresponding to the second width at a second boundary between the filler design and the second area, such that the first marker and the second marker are defined in the intermediate design, and
- store the intermediate design in the storage unit.
A layout design system that receives a chip design requirement and provides a corresponding chip design to a circuit that stores the chip design, the layout design system comprising:
- a processor;
- a storage unit that stores a first standard cell design defining a first active area having a first width, a second standard cell design defining a second active area having a second width different from the first width, and a filler design having no active area;
- a displacement module operating in conjunction with the processor and configured to;
- arrange the first standard cell design in a first area and the second standard cell in a second area to generate an intermediate design in accordance with the chip design requirement, wherein the first area and the second area are separated in the intermediate design by the filler design,
- generate a first marker corresponding to the first width at a first boundary between the filler design and the first area, and a second marker corresponding to the second width at a second boundary between the filler design and the second area, such that the first marker and the second marker are defined in the intermediate design, and
- store the intermediate design in the storage unit.
A layout design system that receives a chip design requirement and provides a corresponding chip design to a circuit that stores the chip design, the layout design system comprising:
- a processor;
- a storage unit that stores a first standard cell design defining a first active area having a first width, a second standard cell design defining a second active area having a second width different from the first width, and a filler design having no active area;
- a displacement module operating in conjunction with the processor and configured to;
- arrange the first standard cell design in a first area and the second standard cell in a second area to generate an intermediate design in accordance with the chip design requirement, wherein the first area and the second area are separated in the intermediate design by the filler design,
- generate a first marker corresponding to the first width at a first boundary between the filler design and the first area, and a second marker corresponding to the second width at a second boundary between the filler design and the second area, such that the first marker and the second marker are defined in the intermediate design.
Dependencies are inferred from the claim text.