Asymmetric mesh NoC topologies

A system, comprising:

• a block placement module configured to determine a size of a two-dimensional mesh reference grid based on dimensions of a chip, dimensions of blocks, and a number of host ports required for each of the blocks of heterogeneous dimensions and overlay the blocks of heterogeneous dimensions on the mesh reference grid based on based on a guidance floor plan for placement of the blocks of heterogeneous dimensions;
• a route construction module configured to:
• remove ones of a plurality routers and corresponding ones of physical links to the ones of the plurality of routers which are blocked by the overlaid blocks of heterogeneous dimensions, based on porosity information of the blocks of heterogeneous dimensions;
• remove redundant series-connected ones of the plurality of routers and merge the physical links associated with the removed redundant series-connected ones of the plurality of routers into a single physical link;
• replace the single physical link with one or more pipeline register stages or one or more buffer stages;
• and
• map inter-block communication over remaining ones of the plurality of routers and physical links of an interconnect for routing messages between blocks;
• and
• a virtual channel allocation module configured to further map the inter-block communication of a network-on-chip architecture by selecting available virtual channels for a physical link such that an entire communication pattern in the network-on-chip architecture is substantially free of cyclic channel dependencies.