System and method for across-chip thermal and power management in stacked IC designs

A computer implemented method comprising:

• accessing a three-dimensional integrated circuit (3D-IC) model stored in a tangible, non-transitory machine readable medium, the model representing a 3D-IC design to be fabricated and to be operated under a condition, the 3D-IC design comprising:
• a plurality of elements in a stack configuration;
• inputting a power profile in a computer processor, the power profile being a function of an operating time and applied to the plurality of elements in the 3D-IC design to be operated under the condition;
• generating a transient temperature profile in the computer processor based on the 3D-IC model, the transient temperature profile including temperatures at a plurality of points of the 3D-IC design as a function of an operating time, based on the 3D-IC design operating under the power input and the condition, wherein each of the plurality of elements in the 3D-IC design is represented as a thermal resistance-capacitance (RC) unit;
• identifying a potential thermal violation at a corresponding operating time interval and a corresponding location of the plurality of points based on the 3D-IC design;
• changing the power profile as a function of the operating time to mitigate the potential thermal violation, based on the data representing the potential thermal violation at the corresponding operating time interval and the corresponding location in the 3D-IC design;
• and
• changing the 3D-IC design to mitigate the potential thermal violation.

A computer implemented system comprising:

• one or more processors;
• and
• at least one tangible, non-transitory machine readable medium encoded with one or more programs, to be executed by the one or more processors, to perform steps of:
• accessing a three-dimensional integrated circuit (3D-IC) model stored in a tangible, non-transitory machine readable medium, the model representing a 3D-IC design to be fabricated and to be operated under a condition, the 3D-IC design comprising:
• a plurality of elements in a stack configuration;
• inputting a power profile in a computer processor, the power profile being a function of an operating time and applied to the plurality of elements in the 3D-IC design to be operated under the condition;
• generating a transient temperature profile in the computer processor based on the 3D-IC model, the transient temperature profile including temperatures at a plurality of points of the 3D-IC design as a function of an operating time, based on the 3D-IC design operating under the power input and the condition, wherein each of the plurality of elements in the 3D-IC design is represented as a thermal resistance-capacitance (RC) unit;
• identifying a potential thermal violation at a corresponding operating time interval and a corresponding location of the plurality of points based on the 3D-IC design;
• outputting data representing the potential thermal violation at the corresponding operating time interval and the corresponding location in the 3D-IC design, and
• changing the power profile as a function of the operating time to mitigate the potential thermal violation.