US 2026/0252771 A1 · System and Method for Simulating Underfill Flow during Packaging of Chip Assembly

Abstract

A system and method for simulating underfill flow during packaging of a chip assembly are provided. The method includes importing an assembly configuration, a bump configuration, and dispensing conditions of an underfill material. A simulation zone is defined based on the assembly configuration, and a corresponding simulation mesh is generated. Bump groups and bump density are determined from the bump configuration to model local flow resistance. The system simulates underfill flow using a thin plate model for confined regions and a porous media model for bump-filled regions, coupled with three-dimensional flow modeling in open areas. Void formation is detected based on the simulated flow results. The hybrid-scale modeling approach provides accurate and efficient prediction of underfill behavior, capillary flow dynamics, and void risks in multi-chip assemblies and fine-pitch semiconductor packaging.

Claims16

Dependent claims

A system for simulating underfill flow during packaging of a chip assembly, comprising:

a memory storing instructions;
a processor coupled to the memory, and configured execute the instruction to:
import an assembly configuration of the chip assembly, a bump configuration of bumps on the chip assembly, and a dispensing condition of an underfill material to be introduced into the chip assembly;
define a simulation zone within the chip assembly based on the assembly configuration;
generate a simulation mesh corresponding to the simulation zone;
determine at least one bump group and a bump density of each bump group based on the bump configuration;
simulate flow of the underfill material into the simulation zone according to a thin plate model defined by the dispensing condition and the assembly configuration, and a porous media model defined by the at least one bump group and the bump density of each bump group;
and
detect formation of voids in the underfill material based on the simulation.

6 more elements

A method for simulating underfill flow during packaging of a chip assembly, comprising:

importing an assembly configuration of the chip assembly, a bump configuration of bumps on the chip assembly, and a dispensing condition of an underfill material to be introduced into the chip assembly;
defining a simulation zone within the chip assembly based on the assembly configuration;
generating a simulation mesh corresponding to the simulation zone;
determining at least one bump group and a bump density of each bump group based on the bump configuration;
simulating flow of the underfill material into the simulation zone according to a thin plate model defined by the dispensing condition and the assembly configuration, and a porous media model defined by the at least one bump group and the bump density of each bump group;
and
detecting formation of voids in the underfill material based on results of the simulation.

4 more elements

Dependencies are inferred from the claim text.

System and Method for Simulating Underfill Flow during Packaging of Chip Assembly

Life of this patent

System and Method for Simulating Underfill Flow during Packaging of Chip Assembly

Life of this patent

Abstract

Claims16