US 12,632,634 B2 · Nanofabrication and design techniques for 3D ICs and configurable ASICs

Abstract

Various embodiments of the present technology provide for the ultra-high density heterogenous integration, enabled by nano-precise pick-and-place assembly. For example, some embodiments provide for the integration of modular assembly techniques with the use of prefabricated blocks (PFBs). These PFBs can be created on one or more sources wafers. Then using pick-and-place technologies, the PFBs can be selectively arranged on a destination wafer thereby allowing Nanoscale-aligned 3D Stacked Integrated Circuit (N3-SI) and the Microscale Modular Assembled ASIC (M2A2) to be efficiently created. Some embodiments include systems and techniques for the construction of construct semiconductor devices which are arbitrarily larger than the standard photolithography field size of 26×33 mm, using pick-and-place assembly.

Claims54

Dependent claims

A method for assembling die onto a product substrate, the method comprising;

selectively picking one or more die from a source wafer by a superstrate attached to said one or more die;
placing and bonding said selectively picked one or more die onto said product substrate with precision overlay, wherein said precision overlay is enabled by a volatile liquid deployed between said one or more die and said product substrate, wherein said volatile liquid comprises one of the following:
isopropyl alcohol and water, wherein said precision overlay comprises a difference between a vector position of points on said one or more die and a vector position of corresponding points on said product substrate;
performing coarse alignment using stage actuators as said selectively picked one or more die are brought to said product substrate;
and
performing fine alignment after said one or more die are touching said volatile liquid deployed between said one or more die and said product substrate.

3 more elements

Dependencies are inferred from the claim text.

Nanofabrication and design techniques for 3D ICs and configurable ASICs

Life of this patent

Nanofabrication and design techniques for 3D ICs and configurable ASICs

Life of this patent

Abstract

Claims54