Asymmetric mesh NoC topologies
AssigneeNetSpeed Systems
InventorsJoji Philip, Sailesh Kumar, Eric Norige, Mahmud Hassan, Sundari Mitra
Life of this patent
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Abstract
Example implementations described herein are directed to a floor plan for a Network on Chip (NoC) topology that can include a plurality of on chip blocks of substantially non-uniform shapes and dimensions. An interconnection network is synthesized along with a plan for a physical layout of the interconnection network based on physical dimensions of the plurality of on chip blocks, the physical dimensions of the floorplan and relative placement information for placing the plurality of on chip blocks on the floorplan. Porosity information for the plurality of on chip blocks on the floorplan and required chip functionality may also be taken into consideration.
Claims12
A method of interconnecting blocks on a floorplan for a Network on Chip (NoC) topology, the method comprising:
- receiving at least physical dimensions of a plurality of on chip blocks on the floorplan
- receiving physical dimensions of the floorplan and relative placement information for placing the plurality of on chip blocks on the floorplan;
- receiving porosity information for the plurality of on chip blocks on the floorplan;
- and
- synthesizing, using a computer, an interconnection network and a plan for a physical layout of the interconnection network for the plurality of on chip blocks on the floorplan based on the received physical dimensions and porosity information and required chip functionality,
- wherein the plurality of on chip blocks comprise on chip blocks of heterogeneous dimensions.
A non-transitory computer readable medium storing instructions for implementing a method, the instructions comprising:
- receiving at least physical dimensions of a plurality of on chip blocks on a floorplan for a Network on Chip (NoC) topology;
- receiving physical dimensions of the floorplan and relative placement information for placing the plurality of on chip blocks on the floorplan;
- receiving porosity information for the plurality of on chip blocks;
- and
- synthesizing an interconnection network and a plan for a physical layout of the interconnection network for the plurality of on chip blocks on the floorplan based on the received physical dimensions and porosity information and required chip functionality, wherein the plurality of on chip blocks comprise blocks of heterogeneous dimensions.
Dependencies are inferred from the claim text.