G01R 31/31704
Design for test
Official title: {Design for test; Design verification (concerning scan tests G01R31/318583; computer-aided design G06F30/00)}
G01R31/31704 (Design for test) appears on 310 US grants and 261 published applications in this corpus.
Search patents in G01R- Granted patents
- 310
- Published applications
- 261
- Assignees
- 137
- Inventors
- 750
- Latest grant
- 17 Feb 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1993 | 4 | 0 |
| 1994 | 2 | 0 |
| 1995 | 1 | 0 |
| 1996 | 11 | 0 |
| 1997 | 3 | 0 |
| 1998 | 6 | 0 |
| 1999 | 9 | 0 |
| 2000 | 2 | 0 |
| 2001 | 6 | 0 |
| 2002 | 9 | 9 |
| 2003 | 6 | 15 |
| 2004 | 7 | 16 |
| 2005 | 15 | 19 |
| 2006 | 18 | 18 |
| 2007 | 12 | 15 |
| 2008 | 10 | 13 |
| 2009 | 12 | 8 |
| 2010 | 12 | 2 |
| 2011 | 13 | 4 |
| 2012 | 7 | 3 |
| 2013 | 4 | 3 |
| 2014 | 9 | 3 |
| 2015 | 5 | 6 |
| 2016 | 7 | 11 |
| 2017 | 6 | 13 |
| 2018 | 12 | 14 |
| 2019 | 20 | 12 |
| 2020 | 17 | 14 |
| 2021 | 14 | 9 |
| 2022 | 13 | 6 |
| 2023 | 13 | 9 |
| 2024 | 14 | 17 |
| 2025 | 9 | 11 |
| 2026 | 2 | 11 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Test for source synchronous interfaces17 Feb 2026US 12,553,942 B2NXP B. V.
- Electric component comparison apparatus, system, and related methods10 Feb 2026US 12,546,833 B2Coilcraft, Incorporated
- Dynamically configurable system-on-chip network30 Dec 2025US 12,510,592 B1Synopsys, Inc.
- Test logic method for an integrated circuit device18 Nov 2025US 12,474,396 B2EM Microelectronic-Marin SA
- Method, system, and non-transitory computer readable medium for verifying pin name18 Nov 2025US 12,474,402 B2Fulian Precision Electronics (Tianjin) Co., LTD.
- Jtag-based soc design verification on emulation1 Oct 2026US 2026/0299020 A1Microsoft Technology Licensing, LLC
- Dual rail memory circuits and methods for forming the same20 Aug 2026US 2026/0245618 A1Taiwan Semiconductor Manufacturing Company.Ltd
- Esd (electrostatic discharge) verification for large io (input/output) arrays25 Jun 2026US 2026/0177611 A1Intel Corporation
- Method and device for predicting wafer test data18 Jun 2026US 2026/0169067 A1DigWise Technology Corporation, LTD
- Systems, Methods, and Devices of Design-For-Test Circuitry30 Apr 2026US 2026/0118420 A1Arm Limited
Most cited
By later US patents
- Method and system for creating and validating low level description of electronic design from higher level, behavior-oriented description, including interactive system for hierarchical display of control and dataflow information324US 5,801,958 ALSI Logic Corporation · 1998
- Method and system for creating, deriving and validating structural description of electronic system from higher level, behavior-oriented description, including interactive schematic design and simulation252US 5,544,067 ALSI Logic Corporation · 1996
- Method and system for creating and validating low level description of electronic design from higher level, behavior-oriented description, including interactive system for hierarchical display of control and dataflow information226US 5,555,201 ALSI Logic Corporation · 1996
- System and method for creating and validating structural description of electronic system219US 5,623,418 ALSI Logic Corporation · 1997
- Method and system for creating, validating, and scaling structural description of electronic device214US 6,216,252 B1LSI Logic Corporation · 2001