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US 12,553,942 B2Granted
Test for source synchronous interfaces
AssigneeNXP B.V.
InventorsAkhil Garg, Sahil Jain, Abhishek Mahajan, Amit Jindal
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Abstract
A method for Design For Test (DFT) for Source Synchronous Interfaces (SSI) includes shifting a test vector into a master register slice with a DFT clock. A functional clock is generated. The test vector and the functional clock are launched from a first SSI of the master register slice. The test vector and the functional clock are captured with a second SSI of a slave. The test vector is shifted out of the slave with the DFT clock.
Claims17
A method for Design For Test (DFT) for Source Synchronous Interfaces (SSI) comprising:
- shifting a test vector into a master register slice with a DFT clock;
- generating a functional clock;
- launching the test vector and the functional clock from a first SSI of the master register slice;
- capturing the test vector and the functional clock with a second SSI of a slave;
- shifting the test vector out of the slave with the DFT clock;
- and propagating the test vector and the functional clock through an intermediate register slice prior to capturing the test vector and the functional clock with the second SSI of the slave, wherein the intermediate register slice is clocked only with the functional clock.
3 more elements
An apparatus comprising:
- a master register slice comprising a first Source Synchronous Interface (SSI);
- a slave comprising a second SSI, wherein the second SSI is configured to receive a test vector and a functional clock from the first SSI during a capture mode;
- and
- a multiplexer connected to the functional clock, a Design For Test (DFT) clock and a clock input of the slave, wherein the multiplexer is configured to select the DFT clock in response to a request to shift out the test vector from the slave and to select the functional clock during the capture mode;
- wherein the test vector and the functional clock propagate through an intermediate register slice prior to being captured with the second SSI of the slave, and the intermediate register slice is clocked only with the functional clock.
2 more elements
An apparatus comprising:
- a first subsystem comprising a first register comprising a first Source Synchronous Interface (SSI);
- a second subsystem comprising a second register comprising a second SSI,
- wherein the second SSI is configured to receive a test vector and a functional clock from the first SSI during a capture mode;
- a multiplexer connected to the functional clock, a Design For Test (DFT) clock and a clock input of the second register, wherein the multiplexer is configured to select the DFT clock in response to a request to shift out the test vector from the second register and to select the functional clock during the capture mode;
- and
- an intermediate register interposed between the first register and the second register, wherein the test vector and the functional clock propagate through the intermediate register prior to being captured with the second SSI, and the intermediate register is clocked only with the functional clock.
3 more elements
Dependencies are inferred from the claim text.