Dual rail memory circuits and methods for forming the same

A circuit, comprising:

• a first input/output (I/O) circuit including:
• a first sense amplifier configured to identify a data bit read out from at least one corresponding first memory cell;
• a first level shifter configured to convert a first data signal from a first voltage domain to a second voltage domain;
• a second level shifter configured to convert a second data signal from the first voltage domain to the second voltage domain;
• a third level shifter configured to convert a third data signal from the second voltage domain to the first voltage domain;
• and
• a first multiplexer operating in the second voltage domain, and configured to select, based on a first control signal, one of a logic combination of the first and second signals or the data bit as the third signal;
• wherein the third level shifter is directly coupled to the first multiplexer.

A method, comprising:

• forming, in a first region of a substrate, a memory array including a plurality of memory cells;
• and
• forming, in a second region of the substrate, a plurality of input/output (I/O) column circuits, the I/O column circuits operatively coupled to the memory array through a plurality of sense amplifiers;
• wherein each of the I/O column circuits comprises a first level shifter, a second level shifter, and a third level shifter;
• wherein each of the first to third level shifters includes a first portion operating with a first voltage domain and a second portion operating with a second voltage domain;
• wherein the respective first portions of the first to third level shifters are formed in a first sub-region of within the second region, and the respective second portions of the first to third level shifters are formed in a second sub-region of the second region;
• and
• wherein the first sub-region and the second sub-region of the second region are separated from each other through only one isolation well.