G01R 31/31701
Arrangements for setting the unit under test [uut] in a test mode
Official title: {Arrangements for setting the Unit Under Test [UUT] in a test mode}
G01R31/31701 (Arrangements for setting the unit under test [uut] in a test mode) appears on 560 US grants and 339 published applications in this corpus.
Search patents in G01R- Granted patents
- 560
- Published applications
- 339
- Assignees
- 199
- Inventors
- 965
- Latest grant
- 16 Jun 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1976 | 1 | 0 |
| 1977 | 0 | 0 |
| 1978 | 0 | 0 |
| 1979 | 0 | 0 |
| 1980 | 1 | 0 |
| 1981 | 0 | 0 |
| 1982 | 1 | 0 |
| 1983 | 1 | 0 |
| 1984 | 1 | 0 |
| 1985 | 5 | 0 |
| 1986 | 5 | 0 |
| 1987 | 4 | 0 |
| 1988 | 4 | 0 |
| 1989 | 7 | 0 |
| 1990 | 10 | 0 |
| 1991 | 13 | 0 |
| 1992 | 16 | 0 |
| 1993 | 8 | 0 |
| 1994 | 21 | 0 |
| 1995 | 20 | 0 |
| 1996 | 15 | 0 |
| 1997 | 10 | 0 |
| 1998 | 18 | 0 |
| 1999 | 25 | 0 |
| 2000 | 13 | 0 |
| 2001 | 18 | 13 |
| 2002 | 10 | 13 |
| 2003 | 19 | 20 |
| 2004 | 13 | 13 |
| 2005 | 16 | 15 |
| 2006 | 15 | 17 |
| 2007 | 11 | 14 |
| 2008 | 16 | 9 |
| 2009 | 12 | 11 |
| 2010 | 14 | 12 |
| 2011 | 12 | 10 |
| 2012 | 8 | 9 |
| 2013 | 4 | 9 |
| 2014 | 10 | 9 |
| 2015 | 13 | 13 |
| 2016 | 20 | 21 |
| 2017 | 11 | 20 |
| 2018 | 21 | 21 |
| 2019 | 18 | 9 |
| 2020 | 18 | 10 |
| 2021 | 20 | 22 |
| 2022 | 20 | 17 |
| 2023 | 18 | 10 |
| 2024 | 13 | 8 |
| 2025 | 8 | 8 |
| 2026 | 3 | 6 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Characterizing path margin monitors without the use of scan chains16 Jun 2026US 12,656,391 B2Synopsys, Inc.
- Solid state ESD SIC simulator3 Mar 2026US 12,566,204 B2FEI Company
- Test mode control circuit, semiconductor apparatus and system, and method thereof10 Feb 2026US 12,546,820 B2SK hynix Inc.
- Integrated circuit chip and die test without cell array28 Oct 2025US 12,456,536 B2SK hynix Inc.
- Reset for scan mode exit for devices with power-on reset generation circuitry2 Sep 2025US 12,405,305 B2STMicroelectronics International N. V.
- Method for determining the gender of a chick18 Jun 2026US 2026/0168980 A1HatchTech Group B.V.
- Voltage droop mitigation during automotive electronics built in self test28 May 2026US 2026/0147039 A1QUALCOMM Incorporated
- System state save and restore mechanism using ram and scan chains9 Apr 2026US 2026/0098900 A1QUALCOMM Incorporated
- System state save and restore mechanism using hold latch cell9 Apr 2026US 2026/0100697 A1QUALCOMM Incorporated
- Reset test system and system-on-chip including the same8 Jan 2026US 2026/0009851 A1Itda Semiconductor Co., Ltd.
Most cited
By later US patents
- Processor condition sensing circuits, systems and methods110US 6,032,268 ATexas Instruments Incorporated · 2000
- Processor condition sensing circuits, systems and methods99US 5,535,331 ATexas Instruments Incorporated · 1996
- Single-chip microprocessor with built-in self-testing function87US 5,657,330 AMitsubishi Denki Kabushiki Kaisha · 1997
- Semiconductor integrated circuit having multiple self-test functions and operating method therefor81US 4,970,727 AMitsubishi Denki Kabushiki Kaisha · 1990
- Forced substrate test mode for packaged integrated circuits77US 5,212,442 AMicron Technology, Inc. · 1993