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US 12,456,536 B2Granted
Integrated circuit chip and die test without cell array
AssigneeSK hynix Inc.
InventorsJi-Hwan Kim, Sang-Muk Oh
Life of this patent
Estimating the term…
Abstract
An integrated circuit chip includes a first through electrode and a second through electrode formed through the integrated circuit chip, a transmission circuit suitable for selecting one of signals transmitted through the first and second through electrodes, respectively, and transmitting the selected signal to a data line, in response to a selection signal, and a selection signal generation circuit suitable for generating the selection signal by toggling the selection signal, during a test operation.
Claims16
A memory system, comprising:
- a substrate;
- a memory controller arranged on the substrate;
- a first integrated circuit chip arranged on the substrate, the first integrated circuit chip including an interface for communicating with the memory controller;
- and
- at least one second integrated circuit chip stacked over the first integrated circuit chip, the at least one second integrated circuit chip electrically coupled with the first integrated circuit chip through a first interconnection and a second interconnection,
- wherein the first integrated circuit chip includes:
- a first data node and a second data node;
- a first latch circuit configured to store data provided from the first data node and data provided through the first interconnection based on a command provided from the memory controller;
- a second latch circuit configured to store data provided from the second data node and data provided through the second interconnection base on the command provided from the memory controller;
- a transmission circuit configured to transmit one of the data of the first latch circuit and the data of the second latch circuit based on a selection signal during a test operation;
- and
- a selection signal generation circuit configured to generate the selection signal based on repair information during a normal operation and configured to toggle the selection signal using a read data strobe signal during the test operation.
9 more elements
A memory system, comprising:
- a substrate;
- a memory controller arranged on the substrate;
- a first integrated circuit chip arranged on the substrate, the first integrated circuit chip including an interface for communicating with the memory controller;
- and
- at least one second integrated circuit chip stacked over the first integrated circuit chip, the at least one second integrated circuit chip electrically coupled with the first integrated circuit chip through a first interconnection and a second interconnection,
- wherein the first integrated circuit chip includes:
- a first interconnection and a second interconnection which are formed in the first integrated circuit chip;
- a transmission circuit configured to, in response to a selection signal, select one of a signal transmitted through the first interconnection and a signal transmitted through the second interconnection and configured to transmit the selected signal to a data line;
- and
- a selection signal generation circuit configured to, during a test operation, generate the selection signal by toggling the selection signal using a read data strobe signal, and generate the selection signal based on repair information during a normal operation.
7 more elements
A memory system, comprising:
- a substrate;
- an interposer formed over the substrate;
- a memory controller formed over the interposer;
- a first integrated circuit chip formed over the interposer, the first integrated circuit chip including an interface for communicating with the memory controller through the interposer;
- and
- at least one second integrated circuit chip stacked over the first integrated circuit chip, the at least one second integrated circuit chip electrically coupled with the first integrated circuit chip through a first interconnection and a second interconnection,
- wherein the first integrated circuit chip includes:
- a selection signal generation circuit configured to generate a selection signal based on repair information during a normal operation and toggle the selection signal using a read data strobe signal during the test operation.
5 more elements
Dependencies are inferred from the claim text.