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US 12,405,305 B2Granted
Reset for scan mode exit for devices with power-on reset generation circuitry
AssigneeSTMicroelectronics International N.V.
InventorShikhar Makkar
Life of this patent
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Abstract
A system for performing scan testing on a device core uses a test access port (TAP). The TAP includes a test clock (TCK) pin, a test data in (TDI) pin, and a test mode select (TMS) pin, along with a test control register (TCR) associated with it. The TCR is used to set a scan mode signal, which configures the scan flip flops within the device core for scan testing and performs the scan testing on the device core. The TCR can also be reset to exit the scan testing, with the reset being triggered by a reset circuit receiving the deassertion of both a scan enable (SE) signal and a scan input (SI) signal during the capture-phase of scan testing.
Claims20
A system, comprising:
- a device core and scan flip flops associated with said device core;
- a test access port (TAP) coupled to the scan flip flops, the TAP having a test clock (TCK) pin configured to receive a test clock (TCK) signal that clocks the TAP, a test data in (TDI) pin configured to receive a test data in (TDI) signal, and a test mode select (TMS) pin configured to receive a test mode select (TMS) signal;
- a test control register (TCR) associated with the TAP;
- wherein the TAP, in response to setting of the TCR to assert a scan mode signal, configures the scan flip flops for a scan testing and performs the scan testing on the device core;
- wherein the TAP, in response to resetting of the TCR to deassert the scan mode signal, exits the scan testing;
- and
- a reset circuit configured to reset the TCR in response to deassertion of both a scan enable (SE) signal applied to the TMS pin and a scan input (SI) signal applied to the TDI pin during a capture-phase of scan testing.
4 more elements
A method of testing a device using a joint test action group (JTAG) test access port (TAP) connected to the device, the method comprising:
- performing a power-on-reset of the device by asserting a power-on reset (POR) signal provided to the TAP;
- resetting a reset circuit in response to assertion of the POR signal;
- resetting a test control register (TCR) in response to assertion of the POR signal;
- exiting power-on-reset by deasserting the POR signal;
- setting the TCR to assert a scan mode signal in response to exit of the power-on-reset;
- asserting a scan enable signal connected to the TAP to cause entry of the device into a shift-phase of a scan mode;
- performing the shift-phase of a scan test in the scan mode;
- deasserting the scan enable signal and asserting a scan in signal to exit the shift-phase of the scan mode and enter a capture-phase of the scan mode;
- pulsing a shift clock and performing the capture-phase of the scan test in the scan mode;
- exiting the scan mode by deasserting the scan enable signal and a scan in signal and pulsing the shift clock to thereby cause assertion of a TCR reset signal;
- and
- resetting the TCR in response to assertion of the TCR reset signal.
9 more elements
An electronic device, comprising:
- a device core and scan flip flops associated with said device core;
- a test access port (TAP) coupled to the scan flip flops, the TAP having a test clock (TCK) pin configured to receive a test clock (TCK) signal that clocks the TAP, a test data in (TDI) pin configured to receive a test data in (TDI) signal, a test mode select (TMS) pin configured to receive a test mode select (TMS) signal;
- a test control register (TCR) associated with the TAP, the TCR having a data input, a reset input configured to receive a TCR reset signal, and a data output;
- a first flip flop having a data input connected to the data output of the TCR, a reset input configured to receive a power-on reset (POR) signal, and a data output;
- a first logic circuit generating a first logic output based upon signals at the TMS and TDI pins and the data output of the first flip flop;
- a second flip flop having a data input coupled to receive the first logic output, a reset input coupled to receive the POR signal, and a data output;
- and
- a second logic circuit configured to assert the TCR reset signal based upon a logical OR operation performed on the data output of the second flip flop.
5 more elements
A system for testing an electronic device, the system comprising:
- a device core;
- a test access port (TAP) connected to the device core, the TAP including a Test Data Input (TDI) pin, a Test Mode Select (TMS) pin, a Test Reset (TRST) pin, a Test Clock (TCK) pin, and a Test Data Output (TDO) pin;
- a reset controller connected to the TRST pin, the reset controller comprising:
- a Test Configuration Register (TCR) configured to hold a logic one or a logic zero and configured to output a scan mode signal to indicate scan test mode or functional mode;
- a first flip-flop having a data input configured to receive the scan mode signal, a data output, and a reset input configured to receive a power-on reset (POR) signal, the first flip-flop being clocked by a TCK signal received at the TCK pin;
- a NOR gate having inputs connected to the TMS and TDI pins and an output;
- an AND gate having inputs connected to the output of the first flip-flop and the output of the NOR gate, and an output;
- a second flip-flop having a data input configured to receive the output of the AND gate, a data output, and a reset input configured to receive the POR signal, the second flip-flop being clocked by the TCK signal;
- and
- an OR gate having inputs connected to the output of the second flip-flop and the POR signal, and an output configured to generate a TCR reset signal to reset the TCR, the TCR reset signal also being provided to the TRST pin of the TAP.
7 more elements
A method for testing a device using a joint test action group (JTAG) test access port (TAP) connected to the device, the method comprising:
- asserting a scan enable signal for device entry into a shift-phase of scan mode;
- performing a shift-phase of a scan test;
- deasserting the scan enable signal and asserting a scan in signal to enter a capture-phase of the scan mode;
- pulsing a shift clock and performing the capture-phase of the scan test;
- and
- exiting the scan mode during the capture-phase by deasserting the scan enable signal and a scan in signal, causing a TCR reset signal assertion to reset a test control register (TCR), wherein reset of the TCR causes the exiting of the scan mode.
3 more elements
Dependencies are inferred from the claim text.