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US 12,546,820 B2Granted
Test mode control circuit, semiconductor apparatus and system, and method thereof
AssigneeSK hynix Inc.
InventorsJin Suk Oh, Young Jae An, Bok Rim Ko, Jae Heung Kim, Min Wook Oh
Life of this patent
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Abstract
A test mode control circuit includes an encryption circuit and a test mode generating circuit. The encryption circuit encrypts, based on an encryption code, an access code set to generate an encrypted access code set. The test mode generating circuit generates a test mode signal based on the encrypted access code set.
Claims19
A test mode control circuit comprising:
- a non-volatile memory configured to store an encrypting code;
- an encrypting circuit configured to:
- receive the encrypting code from the non-volatile memory, and
- change, based on the encrypting code, a logic level of each of at least a part of bits included in an access code set to generate a modified access code set when an encryption function is activated;
- and
- a test mode generating circuit configured to generate a plurality of test mode signals based on the modified access code set.
3 more elements
A semiconductor system comprising:
- an external apparatus configured to provide a control signal corresponding to a decrypted access code set;
- and
- a semiconductor apparatus configured to generate a plurality of test mode signals based on the decrypted access code set,
- wherein the semiconductor apparatus includes:
- an encrypting circuit configured to encrypt the decrypted access code set to generate an encrypted access code set;
- and
- a test mode generating circuit configured to generate the plurality of test mode signals based on the encrypted access code set.
4 more elements
An operating method of a semiconductor system, the operating method comprising:
- providing, by an external apparatus, a control signal corresponding to an access code set for test mode entry;
- entering, by a semiconductor apparatus, a test mode based on the access code set for the test mode entry;
- providing, by the external apparatus, a control signal corresponding to an access code set for generating a test mode signal;
- generating, by the semiconductor apparatus, an encrypted access code set by encrypting the access code set for generating the test mode signal;
- and
- generating, by the semiconductor apparatus, at least one of a plurality of test mode signals based on the encrypted access code set.
3 more elements
Dependencies are inferred from the claim text.