US 2026/0100697 A1 · SYSTEM STATE SAVE AND RESTORE MECHANISM USING HOLD LATCH CELL

Abstract

Aspects of the disclosure are directed to a test mode save and restore operation. In accordance with one aspect, the disclosure includes a hold latch cell configured to execute a save directive for a first operational state of a digital logic system and to execute a restore directive for the first operational state in the digital logic system in an operational mode; a first multiplexer coupled to the hold latch cell, the first multiplexer configured to execute a test sequence on the digital logic system in a test mode; and a logical XOR circuit coupled to the hold latch cell, the logical XOR circuit configured to perform a fault detection on the save directive and the restore directive to generate an error flag signal.

Claims20

Dependent claims

An apparatus comprising:

a hold latch cell configured to execute a save directive for a first operational state of a digital logic system and to execute a restore directive for the first operational state in the digital logic system in an operational mode;
a first multiplexer coupled to the hold latch cell, the first multiplexer configured to execute a test sequence on the digital logic system in a test mode;
and
a logical XOR circuit coupled to the hold latch cell, the logical XOR circuit configured to perform a fault detection on the save directive and the restore directive to generate an error flag signal.

1 more element

Dependencies are inferred from the claim text.

System state save and restore mechanism using hold latch cell

Life of this patent

System state save and restore mechanism using hold latch cell

Life of this patent

Abstract

Claims20