Solid state ESD SIC simulator
AssigneeFEI Company
InventorMarcos Hernandez
Life of this patent
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Abstract
Electrostatic discharge (ESD) test systems include a FET-based pulse generator using pairs of back-to-back FETs coupled to produce an ESD pulse based on discharging a capacitor that is coupled in series with a device under test (DUT). A number of FETs can be selected based on an intended ESD test voltage magnitude.
Claims20
A method, comprising applying an electrostatic discharge (ESD) test pulse to a device-under-test (DUT) by discharging an ESD test capacitor through a back-to-back, series-connected pair of semiconductor-based field effect transistors (FETs) in response to gate pulses applied to gates of the back-to-back, series-connected pair of semiconductor-based FETs.
A method, comprising applying an ESD test pulse to a device-under-test (DUT) by discharging an ESD test capacitor through a back-to-back-connected pair of semiconductor-based field effect transistors (FETs) in response to gate pulses applied to gates of the back-to-back-connected pair of semiconductor-based FETs, wherein the ESD test capacitor is charged with a test voltage source and discharged in response to a control pulse, wherein the control pulse is applied to opto-isolators coupled to respective gates of a first FET and a second FET of the back-to-back-connected pair of semiconductor-based (FETs) to produce the gate pulses, and a plurality of FETs is coupled to the back-to-back-connected pair of semiconductor-based FETs, wherein the ESD test pulse is produced by discharging the ESD capacitor through the plurality of FETs and the back-to-back-connected pair of semiconductor-based FETs.
A method, comprising:
- generating electrostatic discharge (ESD) test pulses with a plurality of ESD pulse generators by discharging respective ESD test capacitors through respective back-to-back-connected pairs of semiconductor-based field effect transistors (FETs) in response to gate pulses applied to gates of the respective back-to-back-connected pair of semiconductor-based FETs;
- and
- selectively coupling the generated ESD test pulses to respective devices under test (DUTs) with a matrix switch.
Dependencies are inferred from the claim text.