Semiconductor integrated circuit having multiple self-test functions and operating method therefor

A method for operating an integrated circuit, said integrated circuit to be tested comprising:

• an input/output means for inputting an outputting data and a special code to specify any of a plurality of special modes for testing said integrated circuit to be tested;
• a control input means for receiving a control signal, a special signal and a confirmation signal;
• detecting means connected to said control input means for detecting said special signal and said confirmation signal applied to said control input means and generating a first detection signal and a second detection signal;
• switching means connected to said input/output;
• latching means connected to said switching means for latching the special code from said input/output means through said switching means,
• said switching means electrically connecting said input/output means to said latching means in response to the first or the second detection signal;
• decoder means connected to said latching means for decoding the special code latched by said latching means and specifying one of said special modes;
• and
• controlling means for executing the special mode specified by said decoder means,
• wherein said input/output means receives the special code latched by said latching means in response to the second detection signal through said switching means and outputs the same to external data lines,
• said method comprising:
• a step of applying a special signal to said detecting means through said control input means;
• a step of applying a confirmation signal to said detecting means through said control input means;
• and
• a step of confirming the special code latched by said latching means at the outside through said input/output means.

A semiconductor memory device comprising:

• a memory array including a plurality of memory cells and means for addressing said plurality of memory cells in said memory array;
• an input/output buffer coupled to a plurality of external data lines and a plurality of control input lines;
• a detection circuit coupled to at least one of said control input lines, wherein said detection circuit detects the presence of a special signal and a confirmation signal applied to said control lines and respectively generates a first detection signal and a second detection signal;
• a switching circuit coupled to said input/output buffer and a latching circuit, wherein said switching circuit electrically connects said input/output buffer to said latching circuit in response to at least one of said first and second detection signals generated by said detection circuit to thereby latch a special code supplied to said input/output buffer via said external data lines;
• a decoder circuit coupled to said latching circuit and a control circuit coupled to said decoder circuit, wherein said decoder circuit decodes the special code latched by said latching circuit and said control means is responsive to the output of said decoder circuit to execute a special mode specified by said special code;
• and
• wherein said input/output buffer transfers said special code to said external data lines in response to said second detecting signal generated by said detecting circuit.