Y10S 438/947
Subphotolithographic processing
Y10S438/947 (Subphotolithographic processing) appears on 513 US grants and 258 published applications in this corpus.
Search patents in Y10S- Granted patents
- 513
- Published applications
- 258
- Assignees
- 116
- Inventors
- 745
- Latest grant
- 7 Oct 2025
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1976 | 1 | 0 |
| 1977 | 10 | 0 |
| 1978 | 0 | 0 |
| 1979 | 0 | 0 |
| 1980 | 1 | 0 |
| 1981 | 2 | 0 |
| 1982 | 6 | 0 |
| 1983 | 3 | 0 |
| 1984 | 7 | 0 |
| 1985 | 3 | 0 |
| 1986 | 3 | 0 |
| 1987 | 3 | 0 |
| 1988 | 4 | 0 |
| 1989 | 8 | 0 |
| 1990 | 3 | 0 |
| 1991 | 7 | 0 |
| 1992 | 3 | 0 |
| 1993 | 10 | 0 |
| 1994 | 12 | 0 |
| 1995 | 12 | 0 |
| 1996 | 11 | 0 |
| 1997 | 27 | 0 |
| 1998 | 23 | 0 |
| 1999 | 25 | 0 |
| 2000 | 28 | 0 |
| 2001 | 25 | 8 |
| 2002 | 26 | 16 |
| 2003 | 17 | 19 |
| 2004 | 18 | 13 |
| 2005 | 13 | 17 |
| 2006 | 16 | 29 |
| 2007 | 18 | 17 |
| 2008 | 13 | 30 |
| 2009 | 19 | 18 |
| 2010 | 27 | 16 |
| 2011 | 20 | 13 |
| 2012 | 27 | 22 |
| 2013 | 11 | 6 |
| 2014 | 20 | 11 |
| 2015 | 13 | 7 |
| 2016 | 4 | 5 |
| 2017 | 4 | 1 |
| 2018 | 1 | 2 |
| 2019 | 2 | 0 |
| 2020 | 1 | 1 |
| 2021 | 1 | 0 |
| 2022 | 1 | 1 |
| 2023 | 1 | 3 |
| 2024 | 1 | 1 |
| 2025 | 2 | 2 |
By publication year. Applications have been published since 2001.
Recent patents
- Semiconductor patterning and resulting structures7 Oct 2025US 12,437,996 B2Taiwan Semiconductor Manufacturing Company.Ltd
- Method for forming patterned mask layer1 Apr 2025US 12,266,528 B2Taiwan Semiconductor Manufacturing Company.Ltd
- Semiconductor patterning and resulting structures12 Mar 2024US 11,929,254 B2Taiwan Semiconductor Manufacturing Company.Ltd
- Method for forming patterned mask layer11 Jul 2023US 11,699,589 B2Taiwan Semiconductor Manufacturing Company.Ltd
- Semiconductor patterning and resulting structures6 Dec 2022US 11,521,856 B2Taiwan Semiconductor Manufacturing Company.Ltd
- Semiconductor patterning and resulting structures23 Oct 2025US 2025/0329533 A1Taiwan Semiconductor Manufacturing Company.Ltd
- Method for forming patterned mask layer19 Jun 2025US 2025/0201562 A1Taiwan Semiconductor Manufacturing Company.Ltd
- Semiconductor Patterning and Resulting Structures30 May 2024US 2024/0177995 A1Taiwan Semiconductor Manufacturing Company.Ltd
- Method for forming patterned mask layer2 Nov 2023US 2023/0352303 A1Taiwan Semiconductor Manufacturing Company.Ltd
- Semiconductor Patterning and Resulting Structures6 Apr 2023US 2023/0108424 A1Taiwan Semiconductor Manufacturing Company.Ltd
Most cited
By later US patents
- Single spacer process for multiplying pitch by a factor greater than two and related intermediate IC structures742US 7,611,980 B2Micron Technology, Inc. · 2009
- Method for manufacturing porous structure and method for forming pattern645US 6,565,763 B1Kabushiki Kaisha Toshiba · 2003
- Method of making dense flash EEPROM cell array and peripheral supporting circuits formed in deposited field oxide with the use of spacers518US 5,661,053 ASanDisk Corporation · 1997
- Method for integrated circuit fabrication using pitch multiplication457US 7,115,525 B2Micron Technology, Inc. · 2006
- Process for fabricating a DRAM array having feature widths that transcend the resolution limit of available photolithography323US 5,013,680 AMicron Technology, Inc. · 1991