US 5,013,680 A · Process for fabricating a DRAM array having feature widths that transcend the resolution limit of available photolithography

Abstract

A process for creating a DRAM array having feature widths that transcend the resolution limit of the employed photolithographic process using only five photomasking steps. The process involves the following steps: creation of a half-pitch hard-material mask that is used to etch a series of equidistanty-spaced isolation trenches in a silicon substrate; filling the isolation trenches with insulative material; creation of a hard-material mask consisting of strips that are 1-1/2F in width, separated by spaces that are 1/2F in width, that is used to etch a matrix of storage trenches; angled implantation of a N-type impurity in the storage trench walls; another anisotropic etch to deepen the storage trenches; deposition of a capacitor dielectric layer; deposition of a protective polysilicon layer on top of the dielectric layer; removal of the dielectric layer and the protective polysilicon layer at the bottom of each storage trench with a further anisotropic etch; filling the storage trenches with in-situ-doped polysilicon; planarization down to the substrate level; creation of an access gate on opposite sides of each storage trench, in addition to wordlines which interconnect gates within array columns by anisotropically etching a conformal conductive layer that has been deposited on top of oxide-silicon mesas that run perpendicular to the isolation trenches and are centered between the rows of storage trenches, the oxide-silicon mesas having been created with an etch using a photoresist mask consisting of a series of parallel strips that have been laid down with minimum feature and space width, then plasma etched to 3/4F; creation of source and drains with an N-type implant; and anisotropically etching the metal layer to create bitlines along the sidewalls of the oxide mesas.

A process for fabricating a dynamic random access memory array on the planarized substrate of a silicon wafer of a first conductivity type, said array having feature widths that transcend the resolution limit of the employed photolithographic process, said process comprising the following steps:

(a) creating a first hard-material mask on the substrate, said first hard-material mask comprising a first series of substantially parallel, hard-material stringers, each of which has both a width of less than F, the minimum feature width of the employed photolithographic process, and also a separation distance, from one or more neighboring stringers in said first series, of less than F;
(b) anisotropically etching the substrate to create a series of substantially parallel isolation trenches in an array region on the wafer;
(c) filling the isolation trenches with insulative material;
(d) replanarizing the wafer back to the substrate level;
(e) creating a second hard-material etch mask on top of the array region comprising a series of substantially parallel, hard-material masking strips with substantially vertical longitudinal edges, each of which is separated from one or more neighboring masking strips, by gaps which are less than or equal to F, said masking strips being substantially perpendicular to said first series of hard-material masking stringers;
(f) etching a matrix of storage trenches in the substrate with an anisotropic etch that is selective for silicon over the insulative material used to fill the isolation trenches, said storage trenches having a pair of substantially vertical, opposing silicon walls and a pair of substantially vertical, opposing insulative-material walls, and said storage trenches being substantially less deep than said isolation trenches;
(g) angled implantation of an impurity which creates junctions of a second conductivity type on the silicon walls of said storage trenches;
(h) deepening said storage trenches with a further anisotropic etch that is selective for silicon over the insulative material, said storage trenches remaining substantially less deep than said isolation trenches;
(i) depositing a dielectric layer on the walls of said storage trenches;
(j) removal of the dielectric layer at the bottom of each storage trench;
(k) filling the storage trenches with polysilicon that is in-situ doped to said first conductivity type;
(l) replanarizing the wafer back to the substrate level;
(m) creating a third series of parallel photoresist strips on the array region, each strip within said third series being substantially perpendicular to the isolation trenches, having a feature width less than or equal to F, and, except at the edges of the array, being substantially centered between a pair of adjacent storage trench rows;
(n) creating a series of wordline mesas having substantially vertical longitudinal edges by anisotropically etching, to substantially equal levels, both silicon and insulative material that is not subjacent one of the photoresist strips of said third series;
(o) stripping said third series of photoresist strips;
(p) creation of a gate oxide layer on top of all exposed silicon;
(q) conformal deposition of a wordline layer;
(r) anisotropically etching said wordline layer to form a wordline stringer on each vertical longitudinal edge of each wordline mesa, the top of each wordline stringer being substantially below wordline mesa height level;
(s) implantation of an impurity which creates source and drain regions of a second conductivity type on exposed silicon surfaces;
(t) deposition of an insulative-material separation layer;
(u) planarizing said separation layer;
(v) masking said separation layer with a fourth series of parallel photoresist strips on the array region, each strip within said fourth series being substantially parallel to the isolation trenches, having a feature width less than or equal to F, and, except at the edges of the array, being substantially centered over an isolation trench and being separated from an adjacent strip within same said series by a gap that is also substantially centered over an isolation trench;
(w) anisotropically etching the separation layer to an extent that the tops of the wordline mesas are cleared, but wordline stringers are not exposed;
(x) deposition of a conformal metal layer;
and
(y) anisotropically etching said metal layer to form bitline stringers.

23 more elements

Process for fabricating a DRAM array having feature widths that transcend the resolution limit of available photolithography

Life of this patent

Process for fabricating a DRAM array having feature widths that transcend the resolution limit of available photolithography

Life of this patent

Abstract

Claims21