Y10S 257/92
Conductor layers on different levels connected in parallel
Official title: Conductor layers on different levels connected in parallel, e.g. to reduce resistance
Y10S257/92 (Conductor layers on different levels connected in parallel) appears on 68 US grants and 32 published applications in this corpus.
Search patents in Y10S- Granted patents
- 68
- Published applications
- 32
- Assignees
- 39
- Inventors
- 103
- Latest grant
- 29 Aug 2023
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1978 | 1 | 0 |
| 1979 | 0 | 0 |
| 1980 | 1 | 0 |
| 1981 | 1 | 0 |
| 1982 | 0 | 0 |
| 1983 | 0 | 0 |
| 1984 | 1 | 0 |
| 1985 | 0 | 0 |
| 1986 | 1 | 0 |
| 1987 | 0 | 0 |
| 1988 | 0 | 0 |
| 1989 | 1 | 0 |
| 1990 | 2 | 0 |
| 1991 | 0 | 0 |
| 1992 | 1 | 0 |
| 1993 | 2 | 0 |
| 1994 | 2 | 0 |
| 1995 | 4 | 0 |
| 1996 | 3 | 0 |
| 1997 | 4 | 0 |
| 1998 | 4 | 0 |
| 1999 | 1 | 0 |
| 2000 | 4 | 0 |
| 2001 | 5 | 1 |
| 2002 | 6 | 4 |
| 2003 | 2 | 6 |
| 2004 | 3 | 1 |
| 2005 | 8 | 3 |
| 2006 | 0 | 0 |
| 2007 | 1 | 2 |
| 2008 | 3 | 12 |
| 2009 | 1 | 0 |
| 2010 | 1 | 0 |
| 2011 | 0 | 1 |
| 2012 | 1 | 0 |
| 2013 | 1 | 0 |
| 2014 | 0 | 0 |
| 2015 | 0 | 0 |
| 2016 | 0 | 0 |
| 2017 | 1 | 1 |
| 2018 | 0 | 0 |
| 2019 | 0 | 0 |
| 2020 | 0 | 0 |
| 2021 | 0 | 0 |
| 2022 | 0 | 0 |
| 2023 | 2 | 1 |
By publication year. Applications have been published since 2001.
Recent patents
- Semiconductor device and production method thereof29 Aug 2023US RE49,631 E1Sony Corporation
- Scalable polylithic on-package integratable apparatus and method28 Feb 2023US RE49,439 E1Intel Corporation
- Scalable polylithic on-package integratable apparatus and method5 Dec 2017US 9,837,391 B2Intel Corporation
- High performance system-on-chip using post passivation process16 Jul 2013US 8,487,400 B2Megica Corporation
- Nonvolatile memory device with recording layer having two portions of different nitrogen amounts7 Aug 2012US 8,237,145 B2Kabushiki Kaisha Toshiba
- A scalable polylithic on-package integratable apparatus and method13 Apr 2023US 2023/0110247 A1Intel Corporation
- Scalable polylithic on-package integratable apparatus and method15 Jun 2017US 2017/0170153 A1Intel Corporation
- Nonvolatile memory device and method for manufacturing same3 Feb 2011US 2011/0024713 A1Kabushiki Kaisha Toshiba
- High performance system-on-chip using post passivation process15 May 2008US 2008/0111243 A1Megica Corporation
- High performance system-on-chip using post passivation process24 Apr 2008US 2008/0093745 A1Megica Corporation
Most cited
By later US patents
- Semiconductor device having built-in high frequency bypass capacitor170US 5,635,767 AMotorola, Inc. · 1997
- Method for forming high performance system-on-chip using post passivation process163US 6,303,423 B1Megic Corporation · 2001
- Circuit arrangement for testing integrated circuit components140US 4,961,053 A1990
- Inductor structure for high performance system-on-chip using post passivation process105US 6,455,885 B1Megic Corporation · 2002
- MOS dynamic ram103US 4,630,088 AKabushiki Kaisha Toshiba · 1986