Scalable polylithic on-package integratable apparatus and method
AssigneeIntel Corporation
InventorsSurhud Khare, Dinesh Somasekhar, Shekhar Y. Borkar
Life of this patent
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Abstract
Described is an apparatus which comprises: a first die including: a processing core; a crossbar switch coupled to the processing core; and a first edge interface coupled to the crossbar switch; and a second die including: a first edge interface positioned at a periphery of the second die and coupled to the first edge interface of the first die, wherein the first edge interface of the first die and the first edge interface of the second die are positioned across each other; a clock synchronization circuit coupled to the second edge interface; and a memory interface coupled to the clock synchronization circuit.
Claims22
An apparatus comprising:
- a first die including:
- a processing core;
- a crossbar switch coupled to the processing core;
- and
- a first edge interface coupled to the crossbar switch;
- and
- a second die including:
- a first edge interface positioned at a periphery of the second die and coupled to the first edge interface of the first die, wherein the first edge interface of the first die and the first edge interface of the second die are positioned across each other;
- a clock synchronization circuit coupled to the second edge interface;
- and
- a memory interface coupled to the clock synchronization circuit.
A method comprising:
- arranging a plurality of first dies each having edge interfaces and crossbar switches;
- arranging a plurality of second dies each having edge interfaces and crossbar switches;
- coupling one or more edge interfaces of at least two of the first dies with one or more edge interfaces of at least two of the second dies;
- coupling a third die with at least one of the first dies, the third die having an edge interface coupled to an edge interface of the at least one of the first die, and having a memory interface;
- and
- coupling a fourth die with at least one of the second dies, the fourth die having an edge interface coupled to an edge interface of the at least one of the second dies, and having a network interface.
Dependencies are inferred from the claim text.