Scalable polylithic on-package integratable apparatus and method
AssigneeIntel Corporation
InventorsSurhud Khare, Dinesh Somasekhar, Shekhar Y. Borkar
Life of this patent
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Abstract
Described is an apparatus which comprises: a first die including: a processing core; a crossbar switch coupled to the processing core; and a first edge interface coupled to the crossbar switch; and a second die including: a first edge interface positioned at a periphery of the second die and coupled to the first edge interface of the first die, wherein the first edge interface of the first die and the first edge interface of the second die are positioned across each other; a clock synchronization circuit coupled to the second edge interface; and a memory interface coupled to the clock synchronization circuit.
Claims28
An apparatus comprising:
- a first die including:
- a processing core;
- a crossbar switch switching circuitry coupled to the processing core;
- and
- a first edge interface coupled to the crossbar switch switching circuitry;
- and
- a second die including:
- a first edge interface positioned at a periphery of the second die and coupled to the first edge interface of the first die, wherein the first edge interface of the first die and the first edge interface of the second die are positioned across each other;
- a clock synchronization circuit coupled to the second edge interface first edge interface of the second die;
- and
- a memory interface coupled to the clock synchronization circuit, wherein the clock synchronization circuit includes circuitry to enable clock domain transitions across the memory interface and the first edge interface of the second die;
- and
- a third die including:
- a first edge interface and a second edge interface, wherein the second edge interface of the third die is coupled to a second edge interface of the first die, wherein the second edge interface of the third die and the second edge interface of the first die are to be positioned across each other.
An apparatus comprising:
- a plurality of heterogeneous dies integrated together in a single polylithic package, the plurality of heterogeneous dies including a number of logic dies and an input-output (IO) die, the logic dies comprising:
- a respective plurality of cores, respective switching circuitry coupled to the plurality of cores, and
- a respective communication interface coupled to the switching circuitry, and
- the IO die comprising:
- an edge interface positioned at a periphery of the IO die;
- a clock synchronization circuit coupled to the edge interface of the IO die;
- and
- a memory interface coupled to the clock synchronization circuit;
- wherein the clock synchronization circuit includes circuitry to enable clock domain transitions across the memory interface and the edge interface of the IO die;
- wherein the edge interface of the IO die is coupled to the communication interface of at least one of the logic dies via a corresponding package-level interconnect;
- and
- wherein at least one edge interface of the IO die and at least one edge interface of one logic die of the logic dies are coupled and positioned across each other.
Dependencies are inferred from the claim text.