H10W 15/01
Manufacture or treatment
Official title: {Manufacture or treatment}
H10W15/01 (Manufacture or treatment) appears on 547 US grants and 277 published applications in this corpus.
Search patents in H10W- Granted patents
- 547
- Published applications
- 277
- Assignees
- 191
- Inventors
- 928
- Latest grant
- 21 Jul 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1976 | 14 | 0 |
| 1977 | 12 | 0 |
| 1978 | 10 | 0 |
| 1979 | 5 | 0 |
| 1980 | 4 | 0 |
| 1981 | 5 | 0 |
| 1982 | 2 | 0 |
| 1983 | 7 | 0 |
| 1984 | 5 | 0 |
| 1985 | 7 | 0 |
| 1986 | 8 | 0 |
| 1987 | 20 | 0 |
| 1988 | 16 | 0 |
| 1989 | 27 | 0 |
| 1990 | 14 | 0 |
| 1991 | 13 | 0 |
| 1992 | 16 | 0 |
| 1993 | 14 | 0 |
| 1994 | 20 | 0 |
| 1995 | 16 | 0 |
| 1996 | 11 | 0 |
| 1997 | 13 | 0 |
| 1998 | 12 | 0 |
| 1999 | 11 | 0 |
| 2000 | 6 | 0 |
| 2001 | 10 | 3 |
| 2002 | 9 | 6 |
| 2003 | 2 | 3 |
| 2004 | 5 | 14 |
| 2005 | 7 | 5 |
| 2006 | 10 | 12 |
| 2007 | 9 | 6 |
| 2008 | 6 | 10 |
| 2009 | 9 | 6 |
| 2010 | 9 | 4 |
| 2011 | 2 | 10 |
| 2012 | 7 | 7 |
| 2013 | 4 | 11 |
| 2014 | 10 | 13 |
| 2015 | 11 | 11 |
| 2016 | 21 | 11 |
| 2017 | 6 | 13 |
| 2018 | 13 | 13 |
| 2019 | 18 | 24 |
| 2020 | 25 | 14 |
| 2021 | 11 | 20 |
| 2022 | 13 | 18 |
| 2023 | 12 | 16 |
| 2024 | 15 | 16 |
| 2025 | 8 | 7 |
| 2026 | 7 | 4 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Embedded semiconductor region for a latch-up susceptibility improvement21 Jul 2026US 12,690,266 B2Taiwan Semiconductor Manufacturing Company.Ltd
- Method of forming semiconductor device23 Jun 2026US 12,666,932 B2Taiwan Semiconductor Manufacturing Company.Ltd
- Integrated structure with trap rich regions and low resistivity regions24 Mar 2026US 12,588,282 B2GLOBALFOUNDRIES U. S. Inc.
- Fabrication of silicon germanium channel and silicon/silicon germanium dual channel field-effect transistors17 Mar 2026US 12,581,719 B2International Business Machines Corporation
- Gate-all-around integrated circuit structures having doped subfin10 Mar 2026US 12,575,151 B2Intel Corporation
- Embedded semiconductor region for latch-up susceptibility improvement8 Oct 2026US 2026/0314060 A1Taiwan Semiconductor Manufacturing Company.Ltd
- Method of forming semiconductor device17 Sep 2026US 2026/0282855 A1Nanya Technology Corporation
- Gate-all-around integrated circuit structures having doped subfin4 Jun 2026US 2026/0156884 A1Intel Corporation
- Hv bcd technology with novel dti structures28 May 2026US 2026/0150639 A1NXP USA, Inc.
- Method of reducing integrated deep trench optically sensitive defectivity2 Oct 2025US 2025/0308980 A1Texas Instruments Incorporated
Most cited
By later US patents
- Process for making a buried conductor by fusing two wafers291US 4,704,785 ATexas Instruments Incorporated · 1987
- Method of making an integrated circuit that combines multi-epitaxial power transistors with logic/analog devices197US 5,034,337 ATexas Instruments Incorporated · 1991
- Vertical field effect transistor and diode197US 6,097,046 ATexas Instruments Incorporated · 2000
- Method for forming pseudo buried layer for sub-micron bipolar or BiCMOS device192US 5,856,003 ATaiwan Semiconductor Manufacturing Company.Ltd · 1999
- Semiconductor device157US 6,037,632 AKabushiki Kaisha Toshiba · 2000