Gate-all-around integrated circuit structures having doped subfin

An integrated circuit structure, comprising:

• a subfin structure;
• a non-conductive layer on the subfin structure, the non-conductive layer comprising silicon and carbon;
• a vertical arrangement of horizontal semiconductor nanowires over the non-conductive layer comprising silicon and carbon, the non-conductive layer comprising silicon and carbon vertically spaced apart from a bottommost nanowire of the vertical arrangement of horizontal semiconductor nanowires;
• a gate stack surrounding a channel region of the vertical arrangement of horizontal semiconductor nanowires, and the gate stack in contact with the non-conductive layer comprising silicon and carbon;
• and
• a pair of epitaxial source or drain structures at first and second ends of the vertical arrangement of horizontal semiconductor nanowires.

A computing device, comprising:

• a board;
• and
• a component coupled to the board, the component including an integrated circuit structure, comprising:
• a subfin structure having well dopants with a concentration of greater than 3E18 atoms/cm3;
• a vertical arrangement of horizontal semiconductor nanowires over the subfin structure;
• a silicon carbide dielectric structure vertically between the vertical arrangement of horizontal semiconductor nanowires and the subfin structure, the silicon carbide dielectric structure vertically spaced apart from a bottommost nanowire of the vertical arrangement of horizontal semiconductor nanowires;
• a gate stack surrounding a channel region of the vertical arrangement of horizontal semiconductor nanowires, wherein the gate stack is in contact with the silicon carbide dielectric structure;
• and
• a pair of epitaxial source or drain structures at first and second ends of the vertical arrangement of horizontal semiconductor nanowires.

A computing device, comprising:

• a board;
• and
• a component coupled to the board, the component including an integrated circuit structure, comprising:
• a subfin structure;
• a non-conductive layer on the subfin structure, the non-conductive layer comprising silicon and carbon;
• a vertical arrangement of horizontal semiconductor nanowires over the non-conductive layer comprising silicon and carbon, the non-conductive layer comprising silicon and carbon vertically spaced apart from a bottommost nanowire of the vertical arrangement of horizontal semiconductor nanowires;
• a gate stack surrounding a channel region of the vertical arrangement of horizontal semiconductor nanowires, and the gate stack in contact with the non-conductive layer comprising silicon and carbon;
• and
• a pair of epitaxial source or drain structures at first and second ends of the vertical arrangement of horizontal semiconductor nanowires.