H10D 89/819

Bias arrangements for gate electrodes of fets

Official title: {Bias arrangements for gate electrodes of FETs, e.g. RC networks or voltage partitioning circuits (FETs in a Darlington configuration H10D89/817)}

H10D89/819 (Bias arrangements for gate electrodes of fets) appears on 444 US grants and 528 published applications in this corpus.

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444
Published applications
528
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205
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854
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18 Aug 2026

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H10D 89/819: granted patents and published applications per publication year
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199610
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200365
200427
2005613
200677
20071016
20081111
2009712
20101414
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2012927
20132222
20142516
20151924
20162523
20171732
20182028
20193732
20202535
20213828
20223046
20233825
20242830
20252530
20261327

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