Electrostatic discharge protection circuit
AssigneeIntegrated Device Technology, Inc.
InventorsChuen-Der Lien, Ta-Ke Tien
Life of this patent
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Abstract
Circuits are disclosed for protecting internal circuitry of a semiconductor chip from increased power supply voltages due to electrostatic discharge (EDS). One example circuit includes a trigger circuit including a transistor and a capacitor arranged in series between DC pads. The trigger circuit generates a trigger signal to a discharge circuit connected between the DC pads to shunt charge from one of the DC pads to the other. The RC delay associated with the transistor and capacitor of the trigger circuit may be designed such that the trigger circuit generates the trigger signal in response to an ESD event, but not in response to high positive spikes on one of the DC pads during normal operation.
Claims33
An electrostatic discharge (ESD) protection circuit comprising:
- a trigger circuit coupled between a first DC pad and a second DC pad, the trigger circuit generating a trigger signal in response to a voltage spike on the first or second DC pad when no DC voltage is present between the first and second DC pads, the trigger circuit not generating a trigger signal in response to a voltage spike on the first or second DC pad when a DC voltage is present between the first and second DC pads, wherein the trigger circuit further comprises a first transistor in series with a capacitor, forming a series circuit coupled between the first and second DC pads;
- and
- a discharge circuit coupled to the trigger circuit to receive the trigger signal, the discharge circuit conducting current between the first and second DC pads in response to the trigger signal.
An electrostatic discharge (ESD) protection circuit, comprising:
- a trigger circuit coupled between a first DC pad and a second DC pad, the trigger circuit generating a trigger signal in response to a voltage spike on the first or second DC pad when no DC voltage is present between the first and second DC pads, the trigger circuit not generating a trigger signal in response to a voltage spike on the first or second DC pad when a DC voltage is present between the first and second DC pads;
- a discharge circuit coupled to the trigger circuit to receive the trigger signal, the discharge circuit conducting current between the first and second DC pads in response to the trigger signal;
- a third DC pad coupled to the trigger circuit;
- the trigger circuit configured to not generate the trigger signal in response to signal on the third DC pad.
An electrostatic discharge (ESD) protection circuit, comprising:
- a trigger circuit coupled between a first DC pad and a second DC pad to detect an ESD event, the trigger circuit comprising a first transistor in series with a first capacitor, forming a series circuit coupled between the first and second DC pads, a terminal of the first transistor generating a trigger signal in response to detection of an ESD event, a gate of the first transistor driven by a delay circuit coupled between the first and second DC pads;
- a discharge circuit coupled to the trigger circuit to receive the trigger signal, the discharge circuit conducting current between the first and second DC pads in response to the trigger signal.
An electrostatic discharge (ESD) protection circuit, comprising:
- a trigger circuit including:
- a first resistor and a first capacitor arranged in series and forming a series circuit between a first DC pad and a second DC pad, the first resistor and the first capacitor being connected at a first node;
- a first transistor and a second capacitor arranged in series between the first and second DC pads, the first transistor and the second capacitor being connected at a second node, a gate of the first transistor being controlled by a signal at the first node;
- a discharge circuit including:
- a driver connected between the first and second DC pads, the driver being controlled by a signal at the second node.
Dependencies are inferred from the claim text.