Voltage control component for ESD protection and its relevant circuitry
AssigneeVanguard International Semiconductor Corporation
InventorsGeeng-Lih Lin, Ming-Dou Ker
Life of this patent
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Abstract
The present invention proposes an ESD protection circuit and its related circuits, suitable in an integrated circuit (IC), and coupled between a first pad and a second pad. When a power supply is provided to the IC, a bias generator generates a bias voltage to close the protection component. When the power supply is not provided to the IC, the protection component is always on to release the ESD stress between the first pad and the second pad.
Claims24
An electrostatic discharge (ESD) protection component, applied on an integrated circuit (IC), coupled between a first connection pad and the second connection pad;
- wherein when a power supply is provided to the IC, the protection component is turned off, and when no power supply is provided to the IC the protection component is on to release ESD stress between the first connection pad and the second connection pad, wherein the protection component is a depletion-mode metal oxide semiconductor (MOS) transistor, and the depletion-mode MOS is a buried-channel component.
An electrostatic discharge (ESD) protection component, applied on an integrated circuit (IC), coupled between a first connection pad and the second connection pad;
- wherein when a power supply is provided to the IC, the protection component is turned off, and when no power supply is provided to the IC the protection component is on to release ESD stress between the first connection pad and the second connection pad, wherein the protection component is a depletion-mode metal oxide semiconductor (MOS) transistor, wherein the depletion-mode MOS is a surface-channel component.
An electrostatic protection (ESD) protection circuit for an integrated circuit (IC), coupled to a first pad and a second pad, comprising:
- an ESD protection component, connected between the first pad and the second pad;
- and
- a bias generator, for turning off the ESD protection component when a power supply is provided to the IC;
- wherein the ESD protection circuit is connected to the first pad through a resistor, when no power supply is provided to the IC, the ESD protection component is always on to release ESD stress between the first pad and the second pad.
The ESD protection component as claimed in claim 8, wherein the ESD protection component is a depletion-mode metal oxide semiconductor (MOS) transistor.
An ESD protection system for an integrated circuit (IC), wherein the IC comprises a plurality of connection pads, Pad1 . . . PadN, the protection system comprising:
- an ESD bus line;
- a plurality of ESD protection component D1 . . . DN, each ESD protection Dn is connected between a correspondent Padn and the ESD bus line;
- and
- a bias generator, for providing a predetermined voltage to close D1 . . . DN when a power supply is provided;
- wherein D1 . . . Dn is on when no power supply is provided to release ESD stress between a Padx and a Pady.
The ESD protection system as claimed in 14, wherein Dn is a depletion-mode metal oxide semiconductor (MOS) transistor.
Dependencies are inferred from the claim text.