US 6,552,886 B1 · Active Vcc-to-Vss ESD clamp with hystersis for low supply chips

Abstract

An electro-static-discharge (ESD) protection circuit is coupled between power and ground. It protects core circuits in a semiconductor chip. The ESD protection circuit is an active circuit that drives the gate of an n-channel clamp transistor. The clamp transistor shunts current from power to ground when its gate is driven high during an ESD event. A voltage divider generates a sense voltage that drives a first inverter. The sense voltage is normally much lower than the switch threshold of the first inverter. When an ESD voltage spike occurs, the sense voltage rises above the switch threshold, switching the output of the first inverter. A string of inverters is driven by the first inverter, with a final inverter driving the gate of the clamp transistor. An extending n-channel transistor drives the input of the final inverter low when the clamping transistor is on, extending the discharge time. A hysteresis p-channel transistor drives the output of the first inverter high, delaying turn-on of the clamp transistor. This increases the voltage required to trigger the protection circuit.

Claims20

Dependent claims

A protection circuit comprising:

a clamping transistor, coupled to shunt current from an electro-static-discharge (ESD) pulse, having a control gate;
a voltage divider, coupled to the ESD pulse, for generating a divided voltage being a predetermined fraction of a voltage of the ESD pulse;
a chain of inverters, receiving the divided voltage, for driving the control gate of the clamping transistor;
and
an extending transistor, for driving an extended internal node in the chain of inverters, having a gate receiving a feedback voltage from another internal node in the chain of inverters after the extended internal node;
whereby the extending transistor extends a discharge time that the clamping transistor is shunting current during the ESD pulse.

3 more elements

A core protection device for protecting core transistors from electro-static-discharge (ESD) pulses comprising:

a clamping n-channel transistor, having a drain coupled to a power supply bus, a source coupled to a ground bus, and a gate coupled to a control node, for shunting current during ESD pulses;
a final inverter receiving an extended node, for outputting the control node;
an extending n-channel transistor, having a drain coupled to the extended node, a source coupled to the ground bus, and a gate coupled to the control node, for extending discharge time when the clamping n-channel transistor is turned on during the ESD pulses;
at least one inverter, receiving a third node, for outputting to the extended node;
a second inverter, receiving a second node, for outputting the third node;
a first inverter, receiving a first node, for outputting the second node;
a first resistor, coupled between the power supply bus and the first node;
and
a second resistor, coupled between the first node and the ground bus;
the first and second resistors for generating a sense voltage on the first node, the sense voltage being proportional to a voltage between the power supply bus and the ground bus;
wherein a switching threshold of the first inverter is lower than the sense voltage when the voltage between the power supply bus and the ground bus is within a normal operating range, the clamping n-channel transistor being turned off;
wherein when the voltage between the power supply bus and the ground bus is above the normal operating range during an ESD pulse, the sense voltage exceeds the switching threshold, and the clamping n-channel transistor is turned on,
whereby discharge time is extended by the extending n-channel transistor.

10 more elements

Dependencies are inferred from the claim text.

Active Vcc-to-Vss ESD clamp with hystersis for low supply chips

Life of this patent

Active Vcc-to-Vss ESD clamp with hystersis for low supply chips

Life of this patent

Abstract

Claims20