Semiconductor biasing circuit

An apparatus comprising:

• a switch coupled between a power input and a power output, the switch having a switch control terminal;
• a semiconductor device including a first semiconductor layer, a second semiconductor layer, and a substrate, the first and second semiconductor layers having dopants of opposite polarities, and the second semiconductor layer and the substrate having dopants of opposite polarities, in which:
• the first semiconductor layer includes a drive circuit, a sense circuit, and a bias circuit;
• the drive circuit has an input and an output, the output of the drive circuit coupled to the switch control terminal;
• the sense circuit has an input and an output, the input of the sense circuit is coupled to the power output, and the output of the sense circuit is coupled to the drive circuit;
• the bias circuit has a first terminal, a second terminal, a third terminal and a fourth terminal, the second terminal is coupled to the power output, and the third terminal is coupled to the second semiconductor layer;
• and
• the bias circuit includes:
• a charge circuit coupled between the first terminal and the third terminal,
• a discharge circuit coupled between the third terminal and the second terminal, and
• a rectifying device coupled between the third terminal and the fourth terminal.

A device comprising:

• a transistor coupled between a power input and a power output, the transistor having a control terminal;
• control and sensing circuitry coupled to the power input, power output, and the control terminal, the control and sensing circuitry being on an isolation tank and a semiconductor substrate;
• and
• a biasing circuit coupled to the power input, the power output, and the isolation tank, the bias circuit configurable to charge the isolation tank responsive to a rising voltage at the power output, discharge the isolation tank responsive to a falling voltage at the power output, and maintain a non-zero voltage at the isolation tank responsive to a negative voltage at the power output.