H10D 64/0131
The additional conductive layer comprising a silicide layer formed by the silicidation
Official title: {the additional conductive layer comprising a silicide layer formed by the silicidation reaction between the layer of silicon with a metal layer which is not formed by metal implantation}
H10D64/0131 (The additional conductive layer comprising a silicide layer formed by the silicidation) appears on 903 US grants and 746 published applications in this corpus.
Search patents in H10D- Granted patents
- 903
- Published applications
- 746
- Assignees
- 212
- Inventors
- 1,623
- Latest grant
- 2 Jun 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1978 | 1 | 0 |
| 1979 | 0 | 0 |
| 1980 | 0 | 0 |
| 1981 | 1 | 0 |
| 1982 | 1 | 0 |
| 1983 | 1 | 0 |
| 1984 | 0 | 0 |
| 1985 | 1 | 0 |
| 1986 | 4 | 0 |
| 1987 | 1 | 0 |
| 1988 | 0 | 0 |
| 1989 | 2 | 0 |
| 1990 | 4 | 0 |
| 1991 | 7 | 0 |
| 1992 | 6 | 0 |
| 1993 | 1 | 0 |
| 1994 | 2 | 0 |
| 1995 | 2 | 0 |
| 1996 | 7 | 0 |
| 1997 | 11 | 0 |
| 1998 | 23 | 0 |
| 1999 | 64 | 0 |
| 2000 | 75 | 0 |
| 2001 | 77 | 17 |
| 2002 | 48 | 53 |
| 2003 | 42 | 32 |
| 2004 | 46 | 39 |
| 2005 | 16 | 60 |
| 2006 | 36 | 58 |
| 2007 | 30 | 55 |
| 2008 | 34 | 60 |
| 2009 | 28 | 50 |
| 2010 | 43 | 29 |
| 2011 | 29 | 26 |
| 2012 | 23 | 15 |
| 2013 | 24 | 30 |
| 2014 | 21 | 22 |
| 2015 | 16 | 25 |
| 2016 | 26 | 24 |
| 2017 | 18 | 17 |
| 2018 | 18 | 21 |
| 2019 | 20 | 20 |
| 2020 | 20 | 16 |
| 2021 | 19 | 22 |
| 2022 | 10 | 19 |
| 2023 | 15 | 14 |
| 2024 | 19 | 8 |
| 2025 | 9 | 9 |
| 2026 | 2 | 5 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Mask layout, semiconductor device and manufacturing method using the same2 Jun 2026US 12,648,204 B2MagnaChip Semiconductor, Ltd.
- Methods for reliably forming microelectronic devices with conductive contacts to silicide regions10 Feb 2026US 12,550,692 B2
- Small grain size polysilicon engineering for threshold voltage mismatch improvement30 Dec 2025US 12,512,322 B2Texas Instruments Incorporated
- Semiconductor device and method of forming the same2 Dec 2025US 12,490,510 B2Taiwan Semiconductor Manufacturing Company.Ltd
- Etching methods for integrated circuits26 Aug 2025US 12,400,873 B2Taiwan Semiconductor Manufacturing Company.Ltd
- Electronic systems with multiple metal nitride liners on conductive contacts above silicide regions18 Jun 2026US 2026/0173831 A1Lodestar Licensing Group LLC
- Semiconductor devices and methods to reduce contact resistivity in semiconductor devices16 Apr 2026US 2026/0107550 A1Tokyo Electron Limited
- Small grain size polysilicon engineering for threshold voltage mismatch improvement26 Mar 2026US 2026/0090050 A1
- High-temperature silicide contact for backside source/drain contacts19 Mar 2026US 2026/0082629 A1QUALCOMM Incorporated
- Extended drain metal oxide semiconductor device5 Mar 2026US 2026/0068279 A1Globalfoundries Singapore Pte. Ltd.
Most cited
By later US patents
- Metal silicidation methods and methods for using same399US 6,127,249 AMicron Technology, Inc. · 2000
- Method of forming a transistor192US 5,908,313 AIntel Corporation · 1999
- Creation of a self-aligned, ion implanted channel region, after source and drain formation186US 5,856,225 AChartered Semiconductor Manufacturing Ltd. · 1999
- Device having spacers for improved salicide resistance on polysilicon gates132US 6,521,964 B1Intel Corporation · 2003
- Device having thin first spacers and partially recessed thick second spacers for improved salicide resistance on polysilicon gates131US 6,509,618 B2Intel Corporation · 2003