Method of forming a transistor
AssigneeIntel Corporation
InventorsRobert S. Chau, Chia-Hong Jan, Paul Packan, Mitchell C. Taylor
Life of this patent
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Abstract
A novel MOS transistor having minimal junction capacitance in this method of fabrication. According to the present invention, a gate dielectric layer is formed on a first surface of the semiconductor substrate. A gate electrode is then formed on the gate dielectric layer. Next, a pair of recesses are formed in the semiconductor substrate on opposite sides of the gate electrode. A dielectric layer is then formed on the surface of each of the recesses. A Semiconductor material is then deposited into the recesses to form a pair of source/drain regions.
Claims16
A method of forming a transistor, said method comprising the steps of:
- forming a gate dielectric layer on a first surface of a semiconductor substrate;
- forming a gate electrode on said gate dielectric layer;
- forming a pair of recesses in said semiconductor substrate in alignment with the outside edges of said gate electrode;
- forming a first semiconductor material in said recesses;
- and
- after forming said first semiconductor material, forming a dielectric layer in said recess beneath said first semiconductor material.
A method of forming a transistor, said method comprising the steps of:
- forming a gate dielectric layer on a first surface of the semiconductor substrate;
- forming a gate electrode on said gate dielectric layer;
- forming a pair of sidewall spacers along opposite sides of said gate electrode;
- forming a pair of recesses in said semiconductor substrate in alignment with the outside edges of said pair of sidewall spacers;
- implanting nitrogen atoms into surface of said pair of recesses;
- selectively depositing semiconductor material onto said nitrogen implanted surface in said pair of recesses to form a pair of source/drain regions;
- and
- annealing said substrate to form a silicon nitride dielectric layer.
A method of forming a transistor comprising the steps of:
- forming a gate dielectric layer on a first surface of the semiconductor substrate;
- forming a gate electrode on said gate dielectric layer;
- forming a pair of recesses in said semiconductor substrate on opposite sides of said gate electrode;
- forming a pair of halo regions through said recesses into said silicon substrate and beneath said gate electrode;
- and
- forming a first semiconductor material in said pair of recesses.
A method of forming a transistor, said method comprising the steps of:
- forming a gate dielectric layer on a first surface of semiconductor substrate;
- forming a gate electrode on said gate dielectric layer;
- forming a pair of sidewall spacers along opposite sides of said gate electrode;
- forming a pair of recesses in said semiconductor substrate in alignment with the outside edges of said pair of sidewall spacers;
- implanting atoms of a first element into said substrate in said pair of recesses;
- selectively depositing semiconductor material onto said substrate in said pair of recesses above said implanted atoms and not onto said sidewall spacers;
- and
- forming a dielectric layer from said atoms of said first element placed into said substrate.
A method of forming a transistor, said method comprising the steps:
- forming a gate dielectric layer on said first surface of said semiconductor substrate;
- forming a gate electrode on said gate dielectric layer;
- forming a pair of sidewall spacers along opposite sides of said gate electrode;
- forming a pair of recesses in said semiconductor substrate in alignment with the outside edges of said pair of sidewall spacers;
- forming a silicon rich dielectric layer onto a surface of said pair of recesses;
- and
- depositing semiconductor material onto said silicon rich dielectric layer in said pair of recesses.
Dependencies are inferred from the claim text.