Small grain size polysilicon engineering for threshold voltage mismatch improvement
AssigneeTexas Instruments Incorporated
InventorsBhaskar Srinivasan, Pushpa Mahalingam, Mahalingam Nandakumar, Mona Eissa, Corinne Gagnet, Christopher Whitesell
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Abstract
A system and method for growing fine grain polysilicon. In one example, the method of forming an integrated circuit includes forming a dielectric layer over a semiconductor substrate, and forming a polysilicon layer over the dielectric layer. The polysilicon layer is formed by a chemical vapor deposition process that includes providing a gas flow including disilane and hydrogen gas over the semiconductor substrate.
Claims26
A method of forming an integrated circuit, comprising:
- forming a dielectric layer over a semiconductor substrate including a MOS transistor area;
- and
- forming a polysilicon layer over the dielectric layer, the forming including a chemical vapor deposition process that includes providing a gas flow including disilane and hydrogen gas over the semiconductor substrate at a pressure in a range from 135 torr to 165 torr.
A method of forming an integrated circuit, comprising:
- forming a source region and a drain region extending into a semiconductor substrate having a top surface;
- forming a dielectric layer over the top surface;
- and
- forming a gate electrode over the dielectric layer and between the source region and the drain region, the gate electrode comprising polysilicon,
- wherein forming the gate electrode includes a chemical vapor deposition (CVD) process that includes providing a gas flow including disilane gas and hydrogen gas over the semiconductor substrate at a pressure in a range from 135 torr to 165 torr.
A method of forming an integrated circuit, comprising:
- forming doped regions having a first conductivity type spaced apart in a semiconductor substrate having an opposite second conductivity type;
- forming a dielectric layer directly on a top surface of the semiconductor substrate;
- and
- forming a polysilicon electrode directly on the dielectric layer and between the doped regions in a deposition chamber,
- wherein forming the polysilicon electrode includes a chemical vapor deposition (CVD) process that provides a gas flow including disilane gas at a flow rate in a range from 50 sccm to 100 sccm and hydrogen at a flow rate in a range from 2500 sccm to 4000 sccm while maintaining a temperature of the semiconductor substrate in a range from 705° C. to 725° C. and a pressure within the deposition chamber in a range from 135 torr to 165 torr.
Dependencies are inferred from the claim text.