H03L 7/197
A time difference being used for locking the loop, the counter counting
Official title: a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division {(H03L7/1806 takes precedence)}
H03L7/197 (A time difference being used for locking the loop, the counter counting) appears on 1,806 US grants and 1,369 published applications in this corpus.
Search patents in H03L- Granted patents
- 1,806
- Published applications
- 1,369
- Assignees
- 537
- Inventors
- 2,603
- Latest grant
- 8 Sep 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1976 | 3 | 0 |
| 1977 | 7 | 0 |
| 1978 | 5 | 0 |
| 1979 | 4 | 0 |
| 1980 | 4 | 0 |
| 1981 | 5 | 0 |
| 1982 | 1 | 0 |
| 1983 | 6 | 0 |
| 1984 | 8 | 0 |
| 1985 | 8 | 0 |
| 1986 | 12 | 0 |
| 1987 | 8 | 0 |
| 1988 | 9 | 0 |
| 1989 | 12 | 0 |
| 1990 | 8 | 0 |
| 1991 | 14 | 0 |
| 1992 | 16 | 0 |
| 1993 | 11 | 0 |
| 1994 | 12 | 0 |
| 1995 | 7 | 0 |
| 1996 | 16 | 0 |
| 1997 | 11 | 0 |
| 1998 | 19 | 0 |
| 1999 | 27 | 0 |
| 2000 | 41 | 0 |
| 2001 | 35 | 18 |
| 2002 | 42 | 67 |
| 2003 | 61 | 47 |
| 2004 | 48 | 56 |
| 2005 | 45 | 69 |
| 2006 | 75 | 77 |
| 2007 | 69 | 67 |
| 2008 | 62 | 75 |
| 2009 | 78 | 73 |
| 2010 | 57 | 48 |
| 2011 | 77 | 62 |
| 2012 | 54 | 48 |
| 2013 | 69 | 45 |
| 2014 | 73 | 53 |
| 2015 | 68 | 46 |
| 2016 | 77 | 62 |
| 2017 | 64 | 41 |
| 2018 | 54 | 59 |
| 2019 | 73 | 65 |
| 2020 | 85 | 58 |
| 2021 | 63 | 48 |
| 2022 | 68 | 53 |
| 2023 | 44 | 43 |
| 2024 | 36 | 29 |
| 2025 | 28 | 30 |
| 2026 | 27 | 30 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Subgroups
Granted patents
Recent patents
- All digital phase-locked loop circuit8 Sep 2026US 12,732,197 B2Sony Semiconductor Solutions Corporation
- Reducing non-linearity in a digital-to-time converter (DTC) when an input clock changes between lower and higher periods8 Sep 2026US 12,732,199 B2Ningbo Aura Semiconductor Co., Limited
- DTC linearization via mismatch-noise cancellation for digital fractional-N PLLs1 Sep 2026US 12,726,212 B2The Regents of the University of California
- High gain detector techniques for low bandwidth low noise phase-locked loops18 Aug 2026US 12,712,551 B2Texas Instruments Incorporated
- Gain calibration of digital-to-time converter (DTC) used in fractional frequency dividers18 Aug 2026US 12,712,553 B2Ningbo Aura Semiconductor Co., Limited
- Serializer and method for operating the same8 Oct 2026US 2026/0312595 A1Taiwan Semiconductor Manufacturing Company.Ltd
- Phase-locked loop and method of operating the same8 Oct 2026US 2026/0312596 A1SK hynix Inc.
- Digital clock frequency tracker and high-speed serial interface chip24 Sep 2026US 2026/0291509 A1Joywell Semiconductor (Shanghai) Co., Ltd.
- Clock generation apparatuses and methods24 Sep 2026US 2026/0291510 A1Intel Corporation
- System and method for phase alignment between multiple phase-locked loops circuits20 Aug 2026US 2026/0246470 A1Movandi Corporation
Most cited
By later US patents
- Digital compensation for wideband modulation of a phase locked loop frequency synthesizer313US 6,008,703 AMassachusetts Institute of Technology · 1999
- Dual-mode satellite/cellular phone with a frequency synthesizer224US 5,535,432 AEricsson GE Mobile Communications Inc. · 1996
- Circuits and methods of implementing time-average-frequency direct period synthesizer on programmable logic chip and driving applications using the same188US 9,621,173 B12017
- Method and apparatus for synchronizing auxiliary data and video data transmitted over a TMDS-like link170US 7,295,578 B12007
- Spread spectrum clock generator and associated method160US 5,488,627 ALexmark International, Inc. · 1996