Phase-locked loop and method of operating the same

A method of operating a phase-locked loop, the method comprising:

• increasing a level of a control voltage when an UP signal is in an enabled state, and decreasing the level of the control voltage when a DOWN signal is in an enabled state;
• generating a first clock signal toggling at a frequency corresponding to the level of the control voltage;
• generating a second reset signal by synchronizing a first reset signal input from an external device with the first clock signal;
• detecting, when both the first reset signal and the second reset signal are in a disabled state, a phase difference between a second clock signal input from an external device and a third clock signal obtained by feeding back the first clock signal, and determining whether to enable each of the UP signal and the DOWN signal;
• maintaining the UP signal in a disabled state and the DOWN signal in an enabled state during a reset preparation period corresponding to a state in which the first reset signal is in a disabled state and the second reset signal is in an enabled state;
• and
• maintaining both the UP signal and the DOWN signal in a disabled state when the both the first reset signal and the second reset signal are in a disabled state.