All digital phase-locked loop circuit

Abstract

All digital phase-locked loop circuits are disclosed. In one example, an all digital phase-locked loop circuit includes a first time-to-digital converter that performs phase difference detection at a first resolution, and a second time-to-digital converter that performs phase difference detection at a second resolution finer than the first resolution and that is arranged in parallel with the first time-to-digital converter. The second time-to-digital converter is configured to allow it to be disabled, and the first time-to-digital converter outputs a clock synchronization selection signal used for synchronizing a reference clock signal to a clock synchronization unit that generates a clock signal of a digital part.

Dependencies are inferred from the claim text.