High gain detector techniques for low bandwidth low noise phase-locked loops

An apparatus comprising:

• a multi-modulus divider (MMD) having a divider input, a divisor input, a first divider output, and a second divider output, the MMD configurable to provide a first pulse signal at the first divider output and a second pulse signal at the second divider output, the first and second pulse signals having a same frequency and different phases;
• a phase detector (PD) having a first clock input, second clock inputs, and a PD output, the second clock inputs coupled to the first and second divider outputs;
• a phase to digital converter (P2DC) having a P2DC input and a P2DC output, the P2DC input coupled to the PD output;
• and
• a delta-sigma modulator having a third clock input, a modulator input, and a modulator output, the third clock input coupled to the first or second divider outputs, the modulator input coupled to the P2DC output, and the modulator output coupled to the divisor input.